/** * @brief Low level serial driver configuration and (re)start. * * @param[in] sdp pointer to a @p SerialDriver object * @param[in] config the architecture-dependent serial driver configuration. * If this parameter is set to @p NULL then a default * configuration is used. * * @notapi */ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { if (config == NULL) config = &default_config; if (sdp->state == SD_STOP) { #if SPC5_SERIAL_USE_LINFLEX0 if (&SD1 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL, SPC5_SERIAL_LINFLEX0_START_PCTL); } #endif #if SPC5_SERIAL_USE_LINFLEX1 if (&SD2 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL, SPC5_SERIAL_LINFLEX1_START_PCTL); } #endif #if SPC5_SERIAL_USE_LINFLEX2 if (&SD3 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL, SPC5_SERIAL_LINFLEX2_START_PCTL); } #endif #if SPC5_SERIAL_USE_LINFLEX3 if (&SD4 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL, SPC5_SERIAL_LINFLEX3_START_PCTL); } #endif } spc5_linflex_init(sdp, config); }
/** * @brief Low level serial driver stop. * * @param[in] sdp pointer to a @p SerialDriver object * * @notapi */ void sd_lld_stop(SerialDriver *sdp) { if (sdp->state == SD_READY) { spc5_linflex_deinit(sdp->linflexp); #if SPC5_SERIAL_USE_LINFLEX0 if (&SD1 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL, SPC5_SERIAL_LINFLEX0_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX1 if (&SD2 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL, SPC5_SERIAL_LINFLEX1_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX2 if (&SD3 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL, SPC5_SERIAL_LINFLEX2_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX3 if (&SD4 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL, SPC5_SERIAL_LINFLEX3_STOP_PCTL); return; } #endif } }
/** * @brief Low level HAL driver initialization. * * @notapi */ void hal_lld_init(void) { uint32_t reg; /* The system is switched to the RUN0 mode, the default for normal operations.*/ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) { SPC5_CLOCK_FAILURE_HOOK(); } /* INTC initialization, software vector mode, 4 bytes vectors, starting at priority 0.*/ INTC.MCR.R = 0; INTC.CPR.R = 0; INTC.IACKR.R = (uint32_t)_vectors; /* PIT channel 0 initialization for Kernel ticks, the PIT is configured to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other modes.*/ INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY; halSPCSetPeripheralClockMode(92, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); reg = halSPCGetSystemClock() / OSAL_ST_FREQUENCY - 1; PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ PIT.CH[0].LDVAL.R = reg; PIT.CH[0].CVAL.R = reg; PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ /* EDMA initialization.*/ edmaInit(); }
/** * @brief Low level HAL driver initialization. * * @notapi */ void hal_lld_init(void) { uint32_t n; /* The system is switched to the RUN0 mode, the default for normal operations.*/ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) { SPC5_CLOCK_FAILURE_HOOK(); } /* PIT_0 clock initialization.*/ halSPCSetPeripheralClockMode(30, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); /* TB counter enabled for debug and measurements.*/ asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */ "mtspr 1008, %%r3" /* HID0 register. */ : : : "r3"); /* PIT channel 0 initialization for Kernel ticks, the PIT is configured to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other modes.*/ INTC_PSR(226) = SPC5_PIT0_IRQ_PRIORITY; n = SPC5_AC12_DC4_CLK / OSAL_ST_FREQUENCY - 1; PIT_0.MCR.R = 1; /* Clock enabled, stop while debugging. */ PIT_0.CH[0].LDVAL.R = n; PIT_0.CH[0].CVAL.R = n; PIT_0.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */ PIT_0.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ /* EDMA initialization.*/ // edmaInit(); }
/** * @brief EDMA driver initialization. * * @special */ void edmaInit(void) { unsigned i; SPC5_EDMA.CR.R = SPC5_EDMA_CR_SETTING; SPC5_EDMA.ERQRL.R = 0x00000000; SPC5_EDMA.EEIRL.R = 0x00000000; SPC5_EDMA.IRQRL.R = 0xFFFFFFFF; SPC5_EDMA.ERL.R = 0xFFFFFFFF; #if SPC5_EDMA_NCHANNELS > 32 SPC5_EDMA.ERQRH.R = 0x00000000; SPC5_EDMA.EEIRH.R = 0x00000000; SPC5_EDMA.IRQRH.R = 0xFFFFFFFF; SPC5_EDMA.ERH.R = 0xFFFFFFFF; #endif /* Initializing all the channels with a different priority withing the channels group.*/ for (i = 0; i < 16; i++) { SPC5_EDMA.CPR[i].R = g0[i]; #if SPC5_EDMA_NCHANNELS > 16 SPC5_EDMA.CPR[i + 16].R = g1[i]; #endif #if SPC5_EDMA_NCHANNELS > 32 SPC5_EDMA.CPR[i + 32].R = g2[i]; SPC5_EDMA.CPR[i + 48].R = g3[i]; #endif } /* Error interrupt source.*/ INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO; #if defined(SPC5_EDMA_MUX_PCTL) /* DMA MUX PCTL setup, only if required.*/ halSPCSetPeripheralClockMode(SPC5_EDMA_MUX_PCTL, SPC5_EDMA_MUX_START_PCTL); #endif }
/** * @brief Low level HAL driver initialization. * * @notapi */ void hal_lld_init(void) { uint32_t n; /* The system is switched to the RUN0 mode, the default for normal operations.*/ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) { SPC5_CLOCK_FAILURE_HOOK(); } #if SPC5_HSM_HANDSHAKE == 1 /* Notifies the HSM full clock initialization.*/ HT2HSMF = 2; #endif #if SPC5_HSM_HANDSHAKE == 2 /* Notifies the HSM full clock initialization by clearing WF_CC_DONE bit * Note that clearing a bit in HSM2HTF mailbox is done by writing 1 in the bit * * We also clear the CLK_CHG_RDY bit, no longer used */ HSM2HTF = WF_CC_DONE | CLK_CHG_RDY; #endif /* PIT_0 clock initialization.*/ halSPCSetPeripheralClockMode(30, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); /* TB counter enabled for debug and measurements.*/ asm volatile ("li %%r3, 0x4000 \t\n" /* TBEN bit. */ "mtspr 1008, %%r3" /* HID0 register. */ : : : "r3"); /* PIT channel 0 initialization for Kernel ticks, the PIT is configured to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other modes.*/ INTC_PSR(226) = SPC5_PIT0_IRQ_PRIORITY; n = SPC5_AC12_DC4_CLK / OSAL_ST_FREQUENCY - 1; PIT_0.MCR.R = 1; /* Clock enabled, stop while debugging. */ PIT_0.TIMER[0].LDVAL.R = n; PIT_0.TIMER[0].CVAL.R = n; PIT_0.TIMER[0].TFLG.R = 1; /* Interrupt flag cleared. */ PIT_0.TIMER[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ /* EDMA initialization.*/ // edmaInit(); }
/** * @brief SPC5xx I/O ports configuration. * * @param[in] config the STM32 ports configuration * * @notapi */ void _pal_lld_init(const PALConfig *config) { unsigned i; #if defined(SPC5_SIUL_PCTL) /* SIUL clock gating if present.*/ halSPCSetPeripheralClockMode(SPC5_SIUL_PCTL, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); #endif /* Initialize PCR registers for undefined pads.*/ for (i = 0; i < SPC5_SIUL_NUM_PCRS; i++) { #if defined(SPC5_SIUL_SYSTEM_PINS) /* Handling the case where some SIU pins are not meant to be reprogrammed, for example JTAG pins.*/ unsigned j; for (j = 0; j < sizeof system_pins; j++) { if (i == system_pins[j]) goto skip; } SIU.PCR[i].R = config->default_mode; skip: ; #else SIU.PCR[i].R = config->default_mode; #endif } /* Initialize PADSEL registers.*/ for (i = 0; i < SPC5_SIUL_NUM_PADSELS; i++) SIU.PSMI[i].R = config->padsels[i]; /* Initialize PCR registers for defined pads.*/ i = 0; while (config->inits[i].pcr_index != -1) { SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value; SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value; i++; } }
/** * @brief SPC5xx I/O ports configuration. * * @param[in] config the SPC5xx ports configuration * * @notapi */ void _pal_lld_init(const PALConfig *config) { unsigned i; #if defined(SPC5_SIUL2_PCTL) /* SIUL clock gating if present.*/ halSPCSetPeripheralClockMode(SPC5_SIUL2_PCTL, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); #endif /* Initialize MSCR_MUX registers.*/ i = 0; while (config->mscr_mux[i].mscr_index != -1) { SIUL2.MSCR_MUX[config->mscr_mux[i].mscr_index].R = config->mscr_mux[i].mscr_value; i++; } /* Initialize MSCR_IO registers for defined pads.*/ i = 0; while (config->mscr_io[i].mscr_index != -1) { SIUL2.GPDO[config->mscr_io[i].mscr_index].R = config->mscr_io[i].gpdo_value; SIUL2.MSCR_IO[config->mscr_io[i].mscr_index].R = config->mscr_io[i].mscr_value; i++; } }
/** * @brief SPC560B/Cxx clocks and PLL initialization. * @note All the involved constants come from the file @p board.h and * @p hal_lld.h * @note This function must be invoked only after the system reset. * * @special */ void spc_clock_init(void) { /* Waiting for IRC stabilization before attempting anything else.*/ while (!ME.GS.B.S_FIRC) ; #if !SPC5_NO_INIT #if SPC5_DISABLE_WATCHDOG /* SWT disabled.*/ SWT.SR.R = 0xC520; SWT.SR.R = 0xD928; SWT.CR.R = 0xFF00000A; #endif /* SSCM initialization. Setting up the most restrictive handling of invalid accesses to peripherals.*/ SSCM.ERROR.R = 3; /* PAE and RAE bits. */ /* RGM errors clearing.*/ RGM.FES.R = 0xFFFF; RGM.DES.R = 0xFFFF; /* Oscillators dividers setup.*/ CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1; CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1; /* The system must be in DRUN mode on entry, if this is not the case then it is considered a serious anomaly.*/ if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) { SPC5_CLOCK_FAILURE_HOOK(); } #if defined(SPC5_OSC_BYPASS) /* If the board is equipped with an oscillator instead of a xtal then the bypass must be activated.*/ CGM.FXOSC_CTL.B.OSCBYP = TRUE; #endif /* SPC5_OSC_BYPASS */ /* Setting the various dividers and source selectors.*/ CGM.SC_DC0.R = SPC5_CGM_SC_DC0; CGM.SC_DC1.R = SPC5_CGM_SC_DC1; CGM.SC_DC2.R = SPC5_CGM_SC_DC2; /* Initialization of the FMPLLs settings.*/ CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF | ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) | (SPC5_FMPLL0_NDIV_VALUE << 16); CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */ /* Run modes initialization.*/ ME.IS.R = 8; /* Resetting I_ICONF status.*/ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */ ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */ ME.HALT.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */ ME.STOP.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */ ME.STANDBY.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */ if (ME.IS.B.I_ICONF) { /* Configuration rejected.*/ SPC5_CLOCK_FAILURE_HOOK(); } /* Peripherals run and low power modes initialization.*/ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS; ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS; ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS; ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS; ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS; ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS; ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS; ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS; ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS; ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS; ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS; ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS; ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS; ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS; ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS; ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS; /* CFLASH settings calculated for a maximum clock of 48MHz.*/ CFLASH.PFCR0.B.BK0_APC = 2; CFLASH.PFCR0.B.BK0_RWSC = 2; /* CMU clock enable */ halSPCSetPeripheralClockMode(104, SPC5_ME_PCTL_RUN(1) | SPC5_ME_PCTL_LP(2)); /* Switches again to DRUN mode (current mode) in order to update the settings.*/ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) { SPC5_CLOCK_FAILURE_HOOK(); } #endif /* !SPC5_NO_INIT */ }
/** * @brief Deactivates the ICU peripheral. * * @param[in] icup pointer to the @p ICUDriver object * * @notapi */ void icu_lld_stop(ICUDriver *icup) { osalDbgAssert(icu_active_submodules0 < 6, "too many submodules"); osalDbgAssert(icu_active_submodules1 < 6, "too many submodules"); osalDbgAssert(icu_active_submodules2 < 6, "too many submodules"); osalDbgAssert(icu_active_submodules3 < 6, "too many submodules"); if (icup->state == ICU_READY) { #if SPC5_ICU_USE_SMOD0 if (&ICUD1 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFE; icu_active_submodules0--; } #endif #if SPC5_ICU_USE_SMOD1 if (&ICUD2 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFD; icu_active_submodules0--; } #endif #if SPC5_ICU_USE_SMOD2 if (&ICUD3 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFB; icu_active_submodules0--; } #endif #if SPC5_ICU_USE_SMOD3 if (&ICUD4 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xF7; icu_active_submodules0--; } #endif #if SPC5_ICU_USE_SMOD4 if (&ICUD5 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xEF; icu_active_submodules0--; } #endif #if SPC5_ICU_USE_SMOD5 if (&ICUD6 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xDF; icu_active_submodules0--; } #endif #if SPC5_ICU_USE_SMOD6 if (&ICUD7 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFE; icu_active_submodules1--; } #endif #if SPC5_ICU_USE_SMOD7 if (&ICUD8 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFD; icu_active_submodules1--; } #endif #if SPC5_ICU_USE_SMOD8 if (&ICUD9 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFB; icu_active_submodules1--; } #endif #if SPC5_ICU_USE_SMOD9 if (&ICUD10 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xF7; icu_active_submodules1--; } #endif #if SPC5_ICU_USE_SMOD10 if (&ICUD11 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xEF; icu_active_submodules1--; } #endif #if SPC5_ICU_USE_SMOD11 if (&ICUD12 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xDF; icu_active_submodules1--; } #endif #if SPC5_ICU_USE_SMOD12 if (&ICUD13 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFE; icu_active_submodules2--; } #endif #if SPC5_ICU_USE_SMOD13 if (&ICUD14 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFD; icu_active_submodules2--; } #endif #if SPC5_ICU_USE_SMOD14 if (&ICUD15 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFB; icu_active_submodules2--; } #endif #if SPC5_ICU_USE_SMOD15 if (&ICUD16 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xF7; icu_active_submodules2--; } #endif #if SPC5_ICU_USE_SMOD16 if (&ICUD17 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xEF; icu_active_submodules2--; } #endif #if SPC5_ICU_USE_SMOD17 if (&ICUD18 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xDF; icu_active_submodules2--; } #endif #if SPC5_ICU_USE_SMOD18 if (&ICUD19 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFE; icu_active_submodules3--; } #endif #if SPC5_ICU_USE_SMOD19 if (&ICUD20 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFD; icu_active_submodules3--; } #endif #if SPC5_ICU_USE_SMOD20 if (&ICUD21 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xFB; icu_active_submodules3--; } #endif #if SPC5_ICU_USE_SMOD21 if (&ICUD22 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xF7; icu_active_submodules3--; } #endif #if SPC5_ICU_USE_SMOD22 if (&ICUD23 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xEF; icu_active_submodules3--; } #endif #if SPC5_ICU_USE_SMOD23 if (&ICUD24 == icup) { /* Disable channel.*/ icup->etimerp->ENBL.B.ENBL &= 0xDF; icu_active_submodules3--; } #endif /* eTimer0 clock deactivation.*/ #if SPC5_ICU_USE_ETIMER0 /* If it is the last active submodules then the eTimer0 is disabled.*/ if (icu_active_submodules0 == 0) { if (icup->etimerp->ENBL.B.ENBL == 0) { halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL, SPC5_ICU_ETIMER0_STOP_PCTL); } } #endif /* eTimer1 clock deactivation.*/ #if SPC5_ICU_USE_ETIMER1 /* If it is the last active submodules then the eTimer1 is disabled.*/ if (icu_active_submodules1 == 0) { if (icup->etimerp->ENBL.B.ENBL == 0) { halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL, SPC5_ICU_ETIMER1_STOP_PCTL); } } #endif /* eTimer2 clock deactivation.*/ #if SPC5_ICU_USE_ETIMER2 /* If it is the last active submodules then the eTimer2 is disabled.*/ if (icu_active_submodules2 == 0) { if (icup->etimerp->ENBL.B.ENBL == 0) { halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL, SPC5_ICU_ETIMER2_STOP_PCTL); } } #endif /* eTimer3 clock deactivation.*/ #if SPC5_ICU_USE_ETIMER3 /* If it is the last active submodules then the eTimer3 is disabled.*/ if (icu_active_submodules3 == 0) { if (icup->etimerp->ENBL.B.ENBL == 0) { halSPCSetPeripheralClockMode(SPC5_ETIMER3_PCTL, SPC5_ICU_ETIMER3_STOP_PCTL); } } #endif } }
/** * @brief Configures and activates the ICU peripheral. * * @param[in] icup pointer to the @p ICUDriver object * * @notapi */ void icu_lld_start(ICUDriver *icup) { osalDbgAssert(icu_active_submodules0 < 6, "too many submodules"); osalDbgAssert(icu_active_submodules1 < 6, "too many submodules"); osalDbgAssert(icu_active_submodules2 < 6, "too many submodules"); osalDbgAssert(icu_active_submodules3 < 6, "too many submodules"); if (icup->state == ICU_STOP) { #if SPC5_ICU_USE_SMOD0 if (&ICUD1 == icup) icu_active_submodules0++; #endif #if SPC5_ICU_USE_SMOD1 if (&ICUD2 == icup) icu_active_submodules0++; #endif #if SPC5_ICU_USE_SMOD2 if (&ICUD3 == icup) icu_active_submodules0++; #endif #if SPC5_ICU_USE_SMOD3 if (&ICUD4 == icup) icu_active_submodules0++; #endif #if SPC5_ICU_USE_SMOD4 if (&ICUD5 == icup) icu_active_submodules0++; #endif #if SPC5_ICU_USE_SMOD5 if (&ICUD6 == icup) icu_active_submodules0++; #endif #if SPC5_ICU_USE_SMOD6 if (&ICUD7 == icup) icu_active_submodules1++; #endif #if SPC5_ICU_USE_SMOD7 if (&ICUD8 == icup) icu_active_submodules1++; #endif #if SPC5_ICU_USE_SMOD8 if (&ICUD9 == icup) icu_active_submodules1++; #endif #if SPC5_ICU_USE_SMOD9 if (&ICUD10 == icup) icu_active_submodules1++; #endif #if SPC5_ICU_USE_SMOD10 if (&ICUD11 == icup) icu_active_submodules1++; #endif #if SPC5_ICU_USE_SMOD11 if (&ICUD12 == icup) icu_active_submodules1++; #endif #if SPC5_ICU_USE_SMOD12 if (&ICUD13 == icup) icu_active_submodules2++; #endif #if SPC5_ICU_USE_SMOD13 if (&ICUD14 == icup) icu_active_submodules2++; #endif #if SPC5_ICU_USE_SMOD14 if (&ICUD15 == icup) icu_active_submodules2++; #endif #if SPC5_ICU_USE_SMOD15 if (&ICUD16 == icup) icu_active_submodules2++; #endif #if SPC5_ICU_USE_SMOD16 if (&ICUD17 == icup) icu_active_submodules2++; #endif #if SPC5_ICU_USE_SMOD17 if (&ICUD18 == icup) icu_active_submodules2++; #endif #if SPC5_ICU_USE_SMOD18 if (&ICUD19 == icup) icu_active_submodules3++; #endif #if SPC5_ICU_USE_SMOD19 if (&ICUD20 == icup) icu_active_submodules3++; #endif #if SPC5_ICU_USE_SMOD20 if (&ICUD21 == icup) icu_active_submodules3++; #endif #if SPC5_ICU_USE_SMOD21 if (&ICUD22 == icup) icu_active_submodules3++; #endif #if SPC5_ICU_USE_SMOD22 if (&ICUD23 == icup) icu_active_submodules3++; #endif #if SPC5_ICU_USE_SMOD23 if (&ICUD24 == icup) icu_active_submodules3++; #endif /* Set eTimer0 Clock.*/ #if SPC5_ICU_USE_ETIMER0 /* If this is the first Submodule activated then the eTimer0 is enabled.*/ if (icu_active_submodules0 == 1) { halSPCSetPeripheralClockMode(SPC5_ETIMER0_PCTL, SPC5_ICU_ETIMER0_START_PCTL); } #endif /* Set eTimer1 Clock.*/ #if SPC5_ICU_USE_ETIMER1 /* If this is the first Submodule activated then the eTimer1 is enabled.*/ if (icu_active_submodules1 == 1) { halSPCSetPeripheralClockMode(SPC5_ETIMER1_PCTL, SPC5_ICU_ETIMER1_START_PCTL); } #endif /* Set eTimer2 Clock.*/ #if SPC5_ICU_USE_ETIMER2 /* If this is the first Submodule activated then the eTimer2 is enabled.*/ if (icu_active_submodules2 == 1) { halSPCSetPeripheralClockMode(SPC5_ETIMER2_PCTL, SPC5_ICU_ETIMER2_START_PCTL); } #endif /* Set eTimer3 Clock.*/ #if SPC5_ICU_USE_ETIMER3 /* If this is the first Submodule activated then the eTimer3 is enabled.*/ if (icu_active_submodules3 == 1) { halSPCSetPeripheralClockMode(SPC5_ETIMER3_PCTL, SPC5_ICU_ETIMER3_START_PCTL); } #endif /* Timer disabled.*/ icup->etimerp->CHANNEL[icup->smod_number].CTRL.B.CNTMODE = SPC5_ETIMER_CNTMODE_NO_OPERATION; /* Clear pending IRQs (if any).*/ icup->etimerp->CHANNEL[icup->smod_number].STS.R = 0xFFFF; /* All IRQs and DMA requests disabled.*/ icup->etimerp->CHANNEL[icup->smod_number].INTDMA.R = 0U; /* Compare Load 1 and Compare Load 2 disabled.*/ icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC1 = 0U; icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CLC2 = 0U; /* Capture 1 and Capture 2 disabled.*/ icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT1MODE = SPC5_ETIMER_CPT1MODE_DISABLED; icup->etimerp->CHANNEL[icup->smod_number].CCCTRL.B.CPT2MODE = SPC5_ETIMER_CPT2MODE_DISABLED; /* Counter reset to zero.*/ icup->etimerp->CHANNEL[icup->smod_number].CNTR.R = 0U; } /* Configuration.*/ spc5_icu_smod_init(icup); }
/** * @brief Deactivates the PWM peripheral. * * @param[in] pwmp pointer to a @p PWMDriver object * * @notapi */ void pwm_lld_stop(PWMDriver *pwmp) { chDbgAssert(flexpwm_active_submodules0 < 5, "pwm_lld_stop(), #1", "too many submodules"); chDbgAssert(flexpwm_active_submodules1 < 5, "pwm_lld_stop(), #2", "too many submodules"); /* If in ready state then disables the PWM clock.*/ if (pwmp->state == PWM_READY) { #if SPC5_PWM_USE_SMOD0 if (&PWMD1 == pwmp) { flexpwm_active_submodules0--; } #endif /* SPC5_PWM_USE_SMOD0 */ #if SPC5_PWM_USE_SMOD1 if (&PWMD2 == pwmp) { flexpwm_active_submodules0--; } #endif /* SPC5_PWM_USE_SMOD1 */ #if SPC5_PWM_USE_SMOD2 if (&PWMD3 == pwmp) { flexpwm_active_submodules0--; } #endif /* SPC5_PWM_USE_SMOD2 */ #if SPC5_PWM_USE_SMOD3 if (&PWMD4 == pwmp) { flexpwm_active_submodules0--; } #endif /* SPC5_PWM_USE_SMOD3 */ #if SPC5_PWM_USE_SMOD4 if (&PWMD5 == pwmp) { flexpwm_active_submodules1--; } #endif /* SPC5_PWM_USE_SMOD4 */ #if SPC5_PWM_USE_SMOD5 if (&PWMD6 == pwmp) { flexpwm_active_submodules1--; } #endif /* SPC5_PWM_USE_SMOD5 */ #if SPC5_PWM_USE_SMOD6 if (&PWMD7 == pwmp) { flexpwm_active_submodules1--; } #endif /* SPC5_PWM_USE_SMOD6 */ #if SPC5_PWM_USE_SMOD7 if (&PWMD8 == pwmp) { flexpwm_active_submodules1--; } #endif /* SPC5_PWM_USE_SMOD7 */ #if SPC5_PWM_USE_SMOD0 if (&PWMD1 == pwmp) { /* SMOD stop.*/ pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U; pwmp->flexpwmp->SUB[0].INTEN.R = 0; pwmp->flexpwmp->SUB[0].STS.R = 0xFFFF; pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE; pwmp->flexpwmp->MCTRL.B.RUN &= 0xE; } #endif #if SPC5_PWM_USE_SMOD1 if (&PWMD2 == pwmp) { /* SMOD stop.*/ pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U; pwmp->flexpwmp->SUB[1].INTEN.R = 0; pwmp->flexpwmp->SUB[1].STS.R = 0xFFFF; pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD; pwmp->flexpwmp->MCTRL.B.RUN &= 0xD; } #endif #if SPC5_PWM_USE_SMOD2 if (&PWMD3 == pwmp) { /* SMOD stop.*/ pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U; pwmp->flexpwmp->SUB[2].INTEN.R = 0; pwmp->flexpwmp->SUB[2].STS.R = 0xFFFF; pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB; pwmp->flexpwmp->MCTRL.B.RUN &= 0xB; } #endif #if SPC5_PWM_USE_SMOD3 if (&PWMD4 == pwmp) { /* SMOD stop.*/ pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U; pwmp->flexpwmp->SUB[3].INTEN.R = 0; pwmp->flexpwmp->SUB[3].STS.R = 0xFFFF; pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7; pwmp->flexpwmp->MCTRL.B.RUN &= 0x7; } #endif #if SPC5_PWM_USE_SMOD4 if (&PWMD5 == pwmp) { /* SMOD stop.*/ pwmp->flexpwmp->MCTRL.B.CLDOK |= 1U; pwmp->flexpwmp->SUB[0].INTEN.R = 0; pwmp->flexpwmp->SUB[0].STS.R = 0xFFFF; pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE; pwmp->flexpwmp->MCTRL.B.RUN &= 0xE; } #endif #if SPC5_PWM_USE_SMOD5 if (&PWMD6 == pwmp) { /* SMOD stop.*/ pwmp->flexpwmp->MCTRL.B.CLDOK |= 2U; pwmp->flexpwmp->SUB[1].INTEN.R = 0; pwmp->flexpwmp->SUB[1].STS.R = 0xFFFF; pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD; pwmp->flexpwmp->MCTRL.B.RUN &= 0xD; } #endif #if SPC5_PWM_USE_SMOD6 if (&PWMD7 == pwmp) { /* SMOD stop.*/ pwmp->flexpwmp->MCTRL.B.CLDOK |= 4U; pwmp->flexpwmp->SUB[2].INTEN.R = 0; pwmp->flexpwmp->SUB[2].STS.R = 0xFFFF; pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB; pwmp->flexpwmp->MCTRL.B.RUN &= 0xB; } #endif #if SPC5_PWM_USE_SMOD7 if (&PWMD8 == pwmp) { /* SMOD stop.*/ pwmp->flexpwmp->MCTRL.B.CLDOK |= 8U; pwmp->flexpwmp->SUB[3].INTEN.R = 0; pwmp->flexpwmp->SUB[3].STS.R = 0xFFFF; pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7; pwmp->flexpwmp->MCTRL.B.RUN &= 0x7; } #endif #if SPC5_PWM_USE_FLEXPWM0 /* Disable peripheral clock if there is not an activated module.*/ if (flexpwm_active_submodules0 == 0) { halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL, SPC5_PWM_FLEXPWM0_STOP_PCTL); } #endif #if SPC5_PWM_USE_FLEXPWM1 /* Disable peripheral clock if there is not an activated module.*/ if (flexpwm_active_submodules1 == 0) { halSPCSetPeripheralClockMode(SPC5_FLEXPWM1_PCTL, SPC5_PWM_FLEXPWM1_STOP_PCTL); } #endif } }
/** * @brief Configures and activates the PWM peripheral. * @note Starting a driver that is already in the @p PWM_READY state * disables all the active channels. * * @param[in] pwmp pointer to a @p PWMDriver object * * @notapi */ void pwm_lld_start(PWMDriver *pwmp) { chDbgAssert(flexpwm_active_submodules0 < 5, "pwm_lld_start(), #1", "too many submodules"); chDbgAssert(flexpwm_active_submodules1 < 5, "pwm_lld_start(), #2", "too many submodules"); if (pwmp->state == PWM_STOP) { #if SPC5_PWM_USE_SMOD0 if (&PWMD1 == pwmp) { flexpwm_active_submodules0++; } #endif /* SPC5_PWM_USE_SMOD0 */ #if SPC5_PWM_USE_SMOD1 if (&PWMD2 == pwmp) { flexpwm_active_submodules0++; } #endif /* SPC5_PWM_USE_SMOD1 */ #if SPC5_PWM_USE_SMOD2 if (&PWMD3 == pwmp) { flexpwm_active_submodules0++; } #endif /* SPC5_PWM_USE_SMOD2 */ #if SPC5_PWM_USE_SMOD3 if (&PWMD4 == pwmp) { flexpwm_active_submodules0++; } #endif /* SPC5_PWM_USE_SMOD3 */ #if SPC5_PWM_USE_SMOD4 if (&PWMD5 == pwmp) { flexpwm_active_submodules1++; } #endif /* SPC5_PWM_USE_SMOD4 */ #if SPC5_PWM_USE_SMOD5 if (&PWMD6 == pwmp) { flexpwm_active_submodules1++; } #endif /* SPC5_PWM_USE_SMOD5 */ #if SPC5_PWM_USE_SMOD6 if (&PWMD7 == pwmp) { flexpwm_active_submodules1++; } #endif /* SPC5_PWM_USE_SMOD6 */ #if SPC5_PWM_USE_SMOD7 if (&PWMD8 == pwmp) { flexpwm_active_submodules1++; } #endif /* SPC5_PWM_USE_SMOD7 */ /** * If this is the first FlexPWM0 submodule * activated then the FlexPWM0 is enabled. */ #if SPC5_PWM_USE_FLEXPWM0 /* Set Peripheral Clock.*/ if (flexpwm_active_submodules0 == 1) { halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL, SPC5_PWM_FLEXPWM0_START_PCTL); } #endif #if SPC5_PWM_USE_FLEXPWM1 /* Set Peripheral Clock.*/ if (flexpwm_active_submodules1 == 1) { halSPCSetPeripheralClockMode(SPC5_FLEXPWM1_PCTL, SPC5_PWM_FLEXPWM1_START_PCTL); } #endif #if SPC5_PWM_USE_SMOD0 if (&PWMD1 == pwmp) { pwm_lld_start_submodule(pwmp, 0); } #endif #if SPC5_PWM_USE_SMOD1 if (&PWMD2 == pwmp) { pwm_lld_start_submodule(pwmp, 1); } #endif #if SPC5_PWM_USE_SMOD2 if (&PWMD3 == pwmp) { pwm_lld_start_submodule(pwmp, 2); } #endif #if SPC5_PWM_USE_SMOD3 if (&PWMD4 == pwmp) { pwm_lld_start_submodule(pwmp, 3); } #endif #if SPC5_PWM_USE_SMOD4 if (&PWMD5 == pwmp) { pwm_lld_start_submodule(pwmp, 0); } #endif #if SPC5_PWM_USE_SMOD5 if (&PWMD6 == pwmp) { pwm_lld_start_submodule(pwmp, 1); } #endif #if SPC5_PWM_USE_SMOD6 if (&PWMD7 == pwmp) { pwm_lld_start_submodule(pwmp, 2); } #endif #if SPC5_PWM_USE_SMOD7 if (&PWMD8 == pwmp) { pwm_lld_start_submodule(pwmp, 3); } #endif } else { /* Driver re-configuration scenario, it must be stopped first.*/ #if SPC5_PWM_USE_SMOD0 if (&PWMD1 == pwmp) { /* Disable the interrupts.*/ pwmp->flexpwmp->SUB[0].INTEN.R = 0; /* Disable the submodule.*/ pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE; /* Active the submodule masks.*/ pwmp->flexpwmp->MASK.B.MASKA &= 0xE; pwmp->flexpwmp->MASK.B.MASKB &= 0xE; /* Sets the MASK registers.*/ pwmp->flexpwmp->SUB[0].CTRL2.B.FRCEN = 1U; pwmp->flexpwmp->SUB[0].CTRL2.B.FORCE = 1U; } #endif #if SPC5_PWM_USE_SMOD1 if (&PWMD2 == pwmp) { /* Disable the interrupts.*/ pwmp->flexpwmp->SUB[1].INTEN.R = 0; /* Disable the submodule.*/ pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD; /* Active the submodule masks.*/ pwmp->flexpwmp->MASK.B.MASKA &= 0xD; pwmp->flexpwmp->MASK.B.MASKB &= 0xD; /* Sets the MASK registers.*/ pwmp->flexpwmp->SUB[1].CTRL2.B.FRCEN = 1U; pwmp->flexpwmp->SUB[1].CTRL2.B.FORCE = 1U; } #endif #if SPC5_PWM_USE_SMOD2 if (&PWMD3 == pwmp) { /* Disable the interrupts.*/ pwmp->flexpwmp->SUB[2].INTEN.R = 0; /* Disable the submodule.*/ pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB; /* Active the submodule masks.*/ pwmp->flexpwmp->MASK.B.MASKA &= 0xB; pwmp->flexpwmp->MASK.B.MASKB &= 0xB; /* Sets the MASK registers.*/ pwmp->flexpwmp->SUB[2].CTRL2.B.FRCEN = 1U; pwmp->flexpwmp->SUB[2].CTRL2.B.FORCE = 1U; } #endif #if SPC5_PWM_USE_SMOD3 if (&PWMD4 == pwmp) { /* Disable the interrupts.*/ pwmp->flexpwmp->SUB[3].INTEN.R = 0; /* Disable the submodule.*/ pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7; /* Active the submodule masks.*/ pwmp->flexpwmp->MASK.B.MASKA &= 0x7; pwmp->flexpwmp->MASK.B.MASKB &= 0x7; /* Sets the MASK registers.*/ pwmp->flexpwmp->SUB[3].CTRL2.B.FRCEN = 1U; pwmp->flexpwmp->SUB[3].CTRL2.B.FORCE = 1U; } #endif #if SPC5_PWM_USE_SMOD4 if (&PWMD5 == pwmp) { /* Disable the interrupts.*/ pwmp->flexpwmp->SUB[0].INTEN.R = 0; /* Disable the submodule.*/ pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xE; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xE; /* Active the submodule masks.*/ pwmp->flexpwmp->MASK.B.MASKA &= 0xE; pwmp->flexpwmp->MASK.B.MASKB &= 0xE; /* Sets the MASK registers.*/ pwmp->flexpwmp->SUB[0].CTRL2.B.FRCEN = 1U; pwmp->flexpwmp->SUB[0].CTRL2.B.FORCE = 1U; } #endif #if SPC5_PWM_USE_SMOD5 if (&PWMD6 == pwmp) { /* Disable the interrupts.*/ pwmp->flexpwmp->SUB[1].INTEN.R = 0; /* Disable the submodule.*/ pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xD; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xD; /* Active the submodule masks.*/ pwmp->flexpwmp->MASK.B.MASKA &= 0xD; pwmp->flexpwmp->MASK.B.MASKB &= 0xD; /* Sets the MASK registers.*/ pwmp->flexpwmp->SUB[1].CTRL2.B.FRCEN = 1U; pwmp->flexpwmp->SUB[1].CTRL2.B.FORCE = 1U; } #endif #if SPC5_PWM_USE_SMOD6 if (&PWMD7 == pwmp) { /* Disable the interrupts.*/ pwmp->flexpwmp->SUB[2].INTEN.R = 0; /* Disable the submodule.*/ pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0xB; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0xB; /* Active the submodule masks.*/ pwmp->flexpwmp->MASK.B.MASKA &= 0xB; pwmp->flexpwmp->MASK.B.MASKB &= 0xB; /* Sets the MASK registers.*/ pwmp->flexpwmp->SUB[2].CTRL2.B.FRCEN = 1U; pwmp->flexpwmp->SUB[2].CTRL2.B.FORCE = 1U; } #endif #if SPC5_PWM_USE_SMOD7 if (&PWMD8 == pwmp) { /* Disable the interrupts.*/ pwmp->flexpwmp->SUB[3].INTEN.R = 0; /* Disable the submodule.*/ pwmp->flexpwmp->OUTEN.B.PWMA_EN &= 0x7; pwmp->flexpwmp->OUTEN.B.PWMB_EN &= 0x7; /* Active the submodule masks.*/ pwmp->flexpwmp->MASK.B.MASKA &= 0x7; pwmp->flexpwmp->MASK.B.MASKB &= 0x7; /* Sets the MASK registers.*/ pwmp->flexpwmp->SUB[3].CTRL2.B.FRCEN = 1U; pwmp->flexpwmp->SUB[3].CTRL2.B.FORCE = 1U; } #endif } }
/** * @brief Low level serial driver stop. * * @param[in] sdp pointer to a @p SerialDriver object * * @notapi */ void sd_lld_stop(SerialDriver *sdp) { if (sdp->state == SD_READY) { spc5_linflex_deinit(sdp->linflexp); #if SPC5_SERIAL_USE_LINFLEX0 if (&SD1 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL, SPC5_SERIAL_LINFLEX0_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX1 if (&SD2 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL, SPC5_SERIAL_LINFLEX1_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX2 if (&SD3 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL, SPC5_SERIAL_LINFLEX2_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX3 if (&SD4 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL, SPC5_SERIAL_LINFLEX3_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX4 if (&SD5 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX4_PCTL, SPC5_SERIAL_LINFLEX4_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX5 if (&SD6 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX5_PCTL, SPC5_SERIAL_LINFLEX5_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX6 if (&SD7 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX6_PCTL, SPC5_SERIAL_LINFLEX6_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX7 if (&SD8 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX7_PCTL, SPC5_SERIAL_LINFLEX7_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX8 if (&SD9 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX8_PCTL, SPC5_SERIAL_LINFLEX8_STOP_PCTL); return; } #endif #if SPC5_SERIAL_USE_LINFLEX9 if (&SD10 == sdp) { halSPCSetPeripheralClockMode(SPC5_LINFLEX9_PCTL, SPC5_SERIAL_LINFLEX9_STOP_PCTL); return; } #endif } }