void hal_reset(void) { // Do any variant-specific reset initialization var_reset(); // Do any platform-specific reset initialization plf_reset(); // Initialize the RAM sections that the rest of the C code requires hal_init_ram_sections(); // All program sections are now in place // Make sure that every instruction above this one has been output by // the compiler HAL_REORDER_BARRIER(); // Now it is safe to use a stack in RAM asm volatile ("lea cyg_interrupt_stack, %sp"); // It is now safe to call C functions which may rely on initialized // data hal_vsr_init(); hal_isr_init(); // Initialize variant HAL private data var_init_data(); // Initialize platform HAL private data plf_init_data(); // Initialize the virtual vector table hal_if_init(); // Call C++ constructors cyg_hal_invoke_constructors(); #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS initialize_stub(); #endif // Init Ctrl-C debug ISR #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) hal_ctrlc_isr_init(); #endif // Call cyg_start. This routine should not return. cyg_start(); }
void hal_platform_init(void) { HAL_WRITE_UINT8(HAL_LED_ADDRESS, cyg_hal_plf_led_val(8)); #if defined(CYG_HAL_STARTUP_ROM) // Note that the hardware seems to come up with the // caches containing random data. Hence they must be // invalidated before being enabled. // However, we only do this if we are in ROM. If we are // in RAM, then we leave the caches in the state chosen // by the ROM monitor. If we enable them when the monitor // is not expecting it, we can end up breaking things if the // monitor is not doing cache flushes. //HAL_ICACHE_INVALIDATE_ALL(); //HAL_ICACHE_ENABLE(); //HAL_DCACHE_INVALIDATE_ALL(); //HAL_DCACHE_ENABLE(); #endif // Set up eCos/ROM interfaces hal_if_init(); #if defined(CYGPKG_KERNEL) && \ defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) { extern void patch_dbg_syscalls(void * vector); patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) ); } #endif #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) { static void hal_ctrlc_isr_init(void); hal_ctrlc_isr_init(); } #endif }
void hal_reset_vsr( void ) { // Call system init routine. This should do the minimum necessary // for the rest of the initialization to complete. For example set // up GPIO, the SRAM, power management etc. This routine is // usually supplied by the platform HAL. Calls to // hal_variant_init() and hal_platform_init() later will perform // the main initialization. hal_system_init(); // Initialize vector table in base of SRAM. { register int i; #if !defined(CYG_HAL_STARTUP_RAM) // Only install the exception vectors for non-RAM startup. For // RAM startup we want these to continue to point to the original // VSRs, which will belong to RedBoot or GDB stubs. for( i = 2; i < 15; i++ ) hal_vsr_table[i] = (CYG_ADDRESS)hal_default_exception_vsr; #endif // Always point SVC and PENDSVC vectors to our local versions hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr; hal_vsr_table[CYGNUM_HAL_VECTOR_PENDSV] = (CYG_ADDRESS)hal_pendable_svc_vsr; // For all startup type, redirect interrupt vectors to our VSR. for( i = CYGNUM_HAL_VECTOR_SYS_TICK ; i < CYGNUM_HAL_VECTOR_SYS_TICK + CYGNUM_HAL_VSR_MAX; i++ ) hal_vsr_table[i] = (CYG_ADDRESS)hal_default_interrupt_vsr; } #if !defined(CYG_HAL_STARTUP_RAM) // Ensure that the CPU will use the vector table we have just set // up. # if defined(CYGHWR_HAL_CORTEXM_M3) // On M3 parts, the NVIC contains a vector table base register. We // program this to relocate the vector table base to the base of // SRAM. HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_VTOR, CYGARC_REG_NVIC_VTOR_TBLOFF(0)| CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM ); # else # error Unknown SRAM/VECTAB remap mechanism # endif // Use SVC to switch our state to thread mode running on the PSP. // We don't need to do this for RAM startup since the ROM code // will have already done it. hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr; __asm__ volatile( "swi" ); hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr; #endif // !defined(CYG_HAL_STARTUP_RAM) #if defined(CYG_HAL_STARTUP_ROM) // Relocate data from ROM to RAM { register cyg_uint32 *p, *q; for( p = &__ram_data_start, q = &__rom_data_start; p < &__ram_data_end; p++, q++ ) *p = *q; } /* // Relocate data from ROM to SRAM { register cyg_uint32 *p, *q; for( p = &__sram_data_start, q = &__srom_data_start; p < &__sram_data_end; p++, q++ ) *p = *q; } */ #endif // Clear BSS { register cyg_uint32 *p; for( p = &__bss_start; p < &__bss_end; p++ ) *p = 0; } // Initialize interrupt vectors. Set the levels for all interrupts // to default values. Also set the default priorities of the // system handlers: all exceptions maximum priority except SVC and // PendSVC which are lowest priority. { register int i; HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR0, 0x00000000 ); HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR1, 0xFF000000 ); HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, 0x00FF0000 ); hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SYS_TICK] = (CYG_ADDRESS)hal_default_isr; for( i = 1; i < CYGNUM_HAL_ISR_COUNT; i++ ) { hal_interrupt_handlers[i] = (CYG_ADDRESS)hal_default_isr; HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(i-CYGNUM_HAL_INTERRUPT_EXTERNAL), 0x80 ); } } #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) // Enable DebugMonitor exceptions. This is needed to enable single // step. This only has an effect if no external JTAG device is // attached. { CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE; cyg_uint32 demcr; HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr ); demcr |= CYGARC_REG_DEBUG_DEMCR_MON_EN; HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr ); } #endif #if !defined(CYG_HAL_STARTUP_RAM) // Enable Usage, Bus and Mem fault handlers. Do this for ROM and // JTAG startups. For RAM startups, this will have already been // done by the ROM monitor. { CYG_ADDRESS base = CYGARC_REG_NVIC_BASE; cyg_uint32 shcsr; HAL_READ_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr ); shcsr |= CYGARC_REG_NVIC_SHCSR_USGFAULTENA; shcsr |= CYGARC_REG_NVIC_SHCSR_BUSFAULTENA; shcsr |= CYGARC_REG_NVIC_SHCSR_MEMFAULTENA; HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr ); } #endif // Call variant and platform init routines hal_variant_init(); hal_platform_init(); // Start up the system clock HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD ); #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS initialize_stub(); #endif #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || \ defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) hal_ctrlc_isr_init(); #endif // Run through static constructors cyg_hal_invoke_constructors(); // Finally call into application cyg_start(); for(;;); }