static int sii9244_power_init(struct sii9244_data *sii9244)
{
int ret;
/* Force the sii9244 into the D0 state. */
ret = tpi_write_reg(sii9244, TPI_DPD_REG, 0x3F);
if (ret < 0)
return ret;
/* Enable TxPLL Clock */
ret = hdmi_rx_write_reg(sii9244, HDMI_RX_TMDS_CLK_EN_REG, 0x01);
if (ret < 0)
return ret;
/* Enable Tx Clock Path & Equalizer*/
ret = hdmi_rx_write_reg(sii9244, HDMI_RX_TMDS_CH_EN_REG, 0x15);
if (ret < 0)
return ret;
/* Power Up TMDS*/
ret = mhl_tx_write_reg(sii9244, 0x08, 0x35);
if (ret < 0)
return ret;
return 0;
}
static void sii9244_hdmi_init(struct sii9244_data *sii9244)
{
/* Analog PLL Control
* bits 5:4 = 2b00 as per characterization team.
*/
hdmi_rx_write_reg(sii9244, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
/* PLL Calrefsel */
hdmi_rx_write_reg(sii9244, HDMI_RX_PLL_CALREFSEL_REG, 0x03);
/* VCO Cal */
hdmi_rx_write_reg(sii9244, HDMI_RX_PLL_VCOCAL_REG, 0x20);
/* Auto EQ */
hdmi_rx_write_reg(sii9244, HDMI_RX_EQ_DATA0_REG, 0x8A);
/* Auto EQ */
hdmi_rx_write_reg(sii9244, HDMI_RX_EQ_DATA1_REG, 0x6A);
/* Auto EQ */
hdmi_rx_write_reg(sii9244, HDMI_RX_EQ_DATA2_REG, 0xAA);
/* Auto EQ */
hdmi_rx_write_reg(sii9244, HDMI_RX_EQ_DATA3_REG, 0xCA);
/* Auto EQ */
hdmi_rx_write_reg(sii9244, HDMI_RX_EQ_DATA4_REG, 0xEA);
/* Manual zone */
hdmi_rx_write_reg(sii9244, HDMI_RX_TMDS_ZONE_CTRL_REG, 0xA0);
/* PLL Mode Value */
hdmi_rx_write_reg(sii9244, HDMI_RX_TMDS_MODE_CTRL_REG, 0x00);
mhl_tx_write_reg(sii9244, MHL_TX_TMDS_CCTRL, 0x34);
hdmi_rx_write_reg(sii9244, 0x45, 0x44);
/* Rx PLL BW ~ 4MHz */
hdmi_rx_write_reg(sii9244, 0x31, 0x0A);
/* Analog PLL Control
* bits 5:4 = 2b00 as per characterization team.
*/
hdmi_rx_write_reg(sii9244, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1);
}
static int sii9234_30pin_reg_init_for_9290(struct sii9234_data *sii9234)
{
int ret = 0;
u8 value;
pr_info("[: %s]++\n", __func__);
ret = tpi_write_reg(sii9234, 0x3D, 0x3F);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x11, 0x01);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x12, 0x15);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x08, 0x35);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x00, 0x00);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x13, 0x60);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x14, 0xF0);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x4B, 0x06);
if (ret < 0)
return ret;
/* Analog PLL Control */
ret = hdmi_rx_write_reg(sii9234, 0x17, 0x07);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x1A, 0x20);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x22, 0xE0);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x23, 0xC0);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x24, 0xA0);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x25, 0x80);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x26, 0x60);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x27, 0x40);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x28, 0x20);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x29, 0x00);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x4D, 0x02);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x4C, 0xA0);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x80, 0x34);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x31, 0x0B);
if (ret < 0)
return ret;
ret = hdmi_rx_write_reg(sii9234, 0x45, 0x06);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0xA0, 0xD0);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0xA1, 0xFC);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0xA3 /*MHL_TX_MHLTX_CTL4_REG*/,
sii9234->pdata->swing_level);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0xA6, 0x00);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x2B, 0x01);
if (ret < 0)
return ret;
/* CBUS & Discovery */
ret = mhl_tx_read_reg(sii9234, 0x90/*MHL_TX_DISC_CTRL1_REG*/, &value);
if (ret < 0)
return ret;
value &= ~(1<<2);
value |= (1<<3);
ret = mhl_tx_write_reg(sii9234, 0x90 /*MHL_TX_DISC_CTRL1_REG*/, value);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x91, 0xE5);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x94, 0x66);
if (ret < 0)
return ret;
ret = cbus_read_reg(sii9234, 0x31, &value);
if (ret < 0)
return ret;
value |= 0x0C;
if (ret < 0)
return ret;
ret = cbus_write_reg(sii9234, 0x31, value);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0xA5, 0x80);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x95, 0x31);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x96, 0x22);
if (ret < 0)
return ret;
ret = mhl_tx_read_reg(sii9234, 0x95/*MHL_TX_DISC_CTRL6_REG*/, &value);
if (ret < 0)
return ret;
value |= (1<<6);
ret = mhl_tx_write_reg(sii9234, 0x95/*MHL_TX_DISC_CTRL6_REG*/, value);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x92, 0x46);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x93, 0xDC);
if (ret < 0)
return ret;
/*0x79=MHL_TX_INT_CTRL_REG*/
ret = mhl_tx_clear_reg(sii9234, 0x79, (1<<2) | (1<<1));
if (ret < 0)
return ret;
mdelay(25);
/*0x95=MHL_TX_DISC_CTRL6_REG*/
ret = mhl_tx_clear_reg(sii9234, 0x95, (1<<6)/*USB_ID_OVR*/);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x90, 0x27);
if (ret < 0)
return ret;
ret = sii9234_cbus_init_for_9290(sii9234);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x05, 0x4);
if (ret < 0)
return ret;
ret = mhl_tx_write_reg(sii9234, 0x0D, 0x1C);
pr_info("[MHD: %s]--\n", __func__);
return ret;
}