void hdmirx_set_hpd(int port, unsigned char val)
{
#ifdef USE_GPIO_FOR_HPD
int bitpos = 1;
switch(port){
case 0:
bitpos=1;
break;
case 1:
bitpos=5;
break;
case 2:
bitpos=9;
break;
case 3:
bitpos=13;
break;
}
if(val){
WRITE_CBUS_REG(PREG_PAD_GPIO5_O, READ_CBUS_REG(PREG_PAD_GPIO5_O) & (~(1<<bitpos)));
}
else{
WRITE_CBUS_REG(PREG_PAD_GPIO5_O, READ_CBUS_REG(PREG_PAD_GPIO5_O) | (1<<bitpos));
}
#else
if(val){
hdmirx_wr_top( HDMIRX_TOP_HPD_PWR5V, hdmirx_rd_top(HDMIRX_TOP_HPD_PWR5V)|(1<<rx.port));
}
else{
hdmirx_wr_top( HDMIRX_TOP_HPD_PWR5V, hdmirx_rd_top(HDMIRX_TOP_HPD_PWR5V)&(~(1<<rx.port)));
}
#endif
hdmirx_print("%s(%d,%d)\n", __func__, port, val);
}
void hdmirx_hw_reset(void)
{
hdmirx_print("%s %d\n", __func__, rx.port);
//WRITE_CBUS_REG(RESET0_REGISTER, 0x8); //reset HDMIRX module
//mdelay(10);
//clk_init();
hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0); //disable top interrupt gate
hdmirx_wr_top( HDMIRX_TOP_SW_RESET, 0x3f);
mdelay(1);
control_reset(0);
hdmirx_wr_top( HDMIRX_TOP_PORT_SEL, (1<<rx.port)); //EDID port select
hdmirx_interrupts_cfg(false); //disable dwc interrupt
if(hdcp_enable){
hdmi_rx_ctrl_hdcp_config(&rx.hdcp);
} else {
hdmirx_wr_bits_dwc( RA_HDCP_CTRL, HDCP_ENABLE, 0);
}
/*phy config*/
//hdmirx_phy_restart();
//hdmi_rx_phy_fast_switching(1);
phy_init(rx.port, 0); //port, dcm
/**/
/* control config */
control_init(rx.port);
audio_init();
packet_init();
hdmirx_audio_fifo_rst();
hdmirx_packet_fifo_rst();
/**/
control_reset(1);
/*enable irq */
hdmirx_wr_top(HDMIRX_TOP_INTR_STAT_CLR, ~0);
hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0x00001fff);
hdmirx_interrupts_hpd(true);
/**/
#ifndef USE_GPIO_FOR_HPD
hdmi_rx_ctrl_hpd(true);
hdmirx_wr_top( HDMIRX_TOP_HPD_PWR5V, (1<<5)|(1<<4)); //invert HDP output
#endif
/* wait at least 4 video frames (at 24Hz) : 167ms for the mode detection
recover the video mode */
mdelay(200);
/* Check If HDCP engine is in Idle state, if not wait for authentication time.
200ms is enough if no Ri errors */
if (hdmirx_rd_dwc(0xe0) != 0)
{
mdelay(200);
}
}
