int hi6xxx_pmic_set_voltage(struct hi6xxx_regulator_vset_regs *vset_regs, unsigned int mask,int shift,int index) { unsigned char value_u8 = 0; unsigned int value_u32 = 0; unsigned long regulator_spin_flag = 0; /* * the spin-lock just for actomic option */ spin_lock_irqsave(®ulator_pmic_spinlock, regulator_spin_flag); /* * though value_u32 is 0,and high 24 bits is 0; * we also only get low 8 bits. */ value_u32 = (unsigned int)hi6xxx_pmic_reg_read(vset_regs->vset_reg)&0xff; BSP_REG_SETBITS(&value_u32,0,shift,mask,index); value_u8 = (unsigned char)value_u32; hi6xxx_pmic_reg_write(vset_regs->vset_reg,value_u8); spin_unlock_irqrestore(®ulator_pmic_spinlock, regulator_spin_flag); return 0; }
static ssize_t freqdump_dbgfs_read(struct seq_file *s, void *p) { int ret = 0; int pos = 0; /* get acpu volt according to PMU_version and transfer to user space*/ if(PMU_VERSION_MIN <= pmu_version) { /*hi6552 pmu chipid*/ acpu_volt_reg = (unsigned int)hi6xxx_pmic_reg_read(SOC_SMART_VSET_BUCK1_ADJ_ADDR(0)); acpu_volt = (800 + 8*acpu_volt_reg)*1000; } else { /*hi6553 pmu chipid*/ acpu_volt_reg = (unsigned int)hi6xxx_pmic_reg_read(SOC_SMART_BUCK01_CTRL3_ADDR(0)); acpu_volt = (600*1000 + 6100*acpu_volt_reg); if (PMU_HI6553_V110 == pmu_version) { acpu_volt += 12200; } } /* copy memory from virt_addr & print to freqdump_buf */ memcpy_fromio(freqdump_tmp, (void *)freqdump_virt_addr, MEMORY_FREQDUMP_SIZE); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_acpu_freq_last); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_acpu_freq_cur); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_acpu_load); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_acpu_core_online); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_every_acpu_load[0]); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_every_acpu_load[1]); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_every_acpu_load[2]); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_every_acpu_load[3]); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_ccpu_freq_last); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_ccpu_freq_cur); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_ccpu_load); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_ddr_freq_last); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_ddr_freq_cur); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u|",freqdump_tmp->freq_ddr_cmd_load); pos += snprintf(freqdump_buf+pos,BUFSZ-pos,"%u",freqdump_tmp->freq_ddr_data_load); /*transfer freqdump message to user space*/ ret = seq_printf(s,"%s\n",freqdump_buf); if (ret < 0) printk(KERN_ERR "seq_printf overflow\n"); return 0; }
int hi6xxx_pmic_get_status(struct hi6xxx_regulator_ctrl_regs *ctrl_regs, unsigned int mask,int shift) { int value_s32 = 0; unsigned char value_u8 = 0; value_u8 = hi6xxx_pmic_reg_read(ctrl_regs->status_reg); /* *the 32 bits only low 8 bits is valid. */ value_s32 = ((int)BSP_REG_GETBITS(&value_u8,0,shift,mask) & 0xff); return !!value_s32; }
unsigned int hi6xxx_pmic_get_voltage_index(struct hi6xxx_regulator_vset_regs *vset_regs,unsigned int mask,int shift) { unsigned int value_u32 = 0; unsigned int ret = 0; /* * though value_u32 is 0,and high 24 bits is 0; * we also only get low 8 bits. */ value_u32 = (unsigned int)hi6xxx_pmic_reg_read(vset_regs->vset_reg)&0xff; ret = ((unsigned int)BSP_REG_GETBITS(&value_u32,0,shift,mask) & 0xff); return ret; }