static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( struct platform_device *pdev) { struct hisi_clock_data *clk_data; int ret; clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS); if (!clk_data) return ERR_PTR(-ENOMEM); ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks, ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), clk_data); if (ret) return ERR_PTR(ret); ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, &clk_data->clk_data); if (ret) goto unregister_gate; return clk_data; unregister_gate: hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), clk_data); return ERR_PTR(ret); }
static void hi3660_clk_crgctrl_init(struct device_node *np) { struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) + ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) + ARRAY_SIZE(hi3660_crgctrl_gate_clks) + ARRAY_SIZE(hi3660_crgctrl_mux_clks) + ARRAY_SIZE(hi3660_crg_fixed_factor_clks) + ARRAY_SIZE(hi3660_crgctrl_divider_clks); clk_data = hisi_clk_init(np, nr); if (!clk_data) return; hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks, ARRAY_SIZE(hi3660_fixed_rate_clks), clk_data); hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks, ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks), clk_data); hisi_clk_register_gate(hi3660_crgctrl_gate_clks, ARRAY_SIZE(hi3660_crgctrl_gate_clks), clk_data); hisi_clk_register_mux(hi3660_crgctrl_mux_clks, ARRAY_SIZE(hi3660_crgctrl_mux_clks), clk_data); hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks, ARRAY_SIZE(hi3660_crg_fixed_factor_clks), clk_data); hisi_clk_register_divider(hi3660_crgctrl_divider_clks, ARRAY_SIZE(hi3660_crgctrl_divider_clks), clk_data); }
static struct hisi_clock_data *hi3798cv200_clk_register( struct platform_device *pdev) { struct hisi_clock_data *clk_data; int ret; clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS); if (!clk_data) return ERR_PTR(-ENOMEM); /* hisi_phase_clock is resource managed */ ret = hisi_clk_register_phase(&pdev->dev, hi3798cv200_phase_clks, ARRAY_SIZE(hi3798cv200_phase_clks), clk_data); if (ret) return ERR_PTR(ret); ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks, ARRAY_SIZE(hi3798cv200_fixed_rate_clks), clk_data); if (ret) return ERR_PTR(ret); ret = hisi_clk_register_mux(hi3798cv200_mux_clks, ARRAY_SIZE(hi3798cv200_mux_clks), clk_data); if (ret) goto unregister_fixed_rate; ret = hisi_clk_register_gate(hi3798cv200_gate_clks, ARRAY_SIZE(hi3798cv200_gate_clks), clk_data); if (ret) goto unregister_mux; ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, &clk_data->clk_data); if (ret) goto unregister_gate; return clk_data; unregister_gate: hisi_clk_unregister_gate(hi3798cv200_gate_clks, ARRAY_SIZE(hi3798cv200_gate_clks), clk_data); unregister_mux: hisi_clk_unregister_mux(hi3798cv200_mux_clks, ARRAY_SIZE(hi3798cv200_mux_clks), clk_data); unregister_fixed_rate: hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, ARRAY_SIZE(hi3798cv200_fixed_rate_clks), clk_data); return ERR_PTR(ret); }
static void hi3660_clk_pctrl_init(struct device_node *np) { struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks); clk_data = hisi_clk_init(np, nr); if (!clk_data) return; hisi_clk_register_gate(hi3660_pctrl_gate_clks, ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data); }
static void __init hi6220_clk_power_init(struct device_node *np) { struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS); if (!clk_data) return; hisi_clk_register_gate(hi6220_gate_clks_power, ARRAY_SIZE(hi6220_gate_clks_power), clk_data); hi6220_clk_register_divider(hi6220_div_clks_power, ARRAY_SIZE(hi6220_div_clks_power), clk_data); }
static void __init hi6220_clk_sys_init(struct device_node *np) { struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS); if (!clk_data) return; hisi_clk_register_gate(hi6220_reset_clks, ARRAY_SIZE(hi6220_reset_clks), clk_data); hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys, ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data); hisi_clk_register_mux(hi6220_mux_clks_sys, ARRAY_SIZE(hi6220_mux_clks_sys), clk_data); hi6220_clk_register_divider(hi6220_div_clks_sys, ARRAY_SIZE(hi6220_div_clks_sys), clk_data); }