static void avm_a1p_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val, sval; if (!cs) { printk(KERN_WARNING "AVM A1 PCMCIA: Spurious interrupt!\n"); return; } while ((sval = (~bytein(cs->hw.avm.cfg_reg+ASL0_OFFSET) & ASL0_R_IRQPENDING))) { if (cs->debug & L1_DEB_INTSTAT) debugl1(cs, "avm IntStatus %x", sval); if (sval & ASL0_R_HSCX) { val = ReadHSCX(cs, 1, HSCX_ISTA); if (val) hscx_int_main(cs, val); } if (sval & ASL0_R_ISAC) { val = ReadISAC(cs, ISAC_ISTA); if (val) isac_interrupt(cs, val); } } WriteHSCX(cs, 0, HSCX_MASK, 0xff); WriteHSCX(cs, 1, HSCX_MASK, 0xff); WriteISAC(cs, ISAC_MASK, 0xff); WriteISAC(cs, ISAC_MASK, 0x00); WriteHSCX(cs, 0, HSCX_MASK, 0x00); WriteHSCX(cs, 1, HSCX_MASK, 0x00); }
static void sportster_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val; if (!cs) { printk(KERN_WARNING "Sportster: Spurious interrupt!\n"); return; } val = READHSCX(cs, 1, HSCX_ISTA); Start_HSCX: if (val) hscx_int_main(cs, val); val = ReadISAC(cs, ISAC_ISTA); Start_ISAC: if (val) isac_interrupt(cs, val); val = READHSCX(cs, 1, HSCX_ISTA); if (val) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = ReadISAC(cs, ISAC_ISTA); if (val) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } /* get a new irq impulse if there any pending */ bytein(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ +1); }
static void gazel_interrupt(int intno, void *dev_id, struct pt_regs *regs) { #define MAXCOUNT 5 struct IsdnCardState *cs = dev_id; u_char valisac, valhscx; int count = 0; if (!cs) { printk(KERN_WARNING "Gazel: Spurious interrupt!\n"); return; } do { valhscx = ReadHSCX(cs, 1, HSCX_ISTA); if (valhscx) hscx_int_main(cs, valhscx); valisac = ReadISAC(cs, ISAC_ISTA); if (valisac) isac_interrupt(cs, valisac); count++; } while ((valhscx || valisac) && (count < MAXCOUNT)); WriteHSCX(cs, 0, HSCX_MASK, 0xFF); WriteHSCX(cs, 1, HSCX_MASK, 0xFF); WriteISAC(cs, ISAC_MASK, 0xFF); WriteISAC(cs, ISAC_MASK, 0x0); WriteHSCX(cs, 0, HSCX_MASK, 0x0); WriteHSCX(cs, 1, HSCX_MASK, 0x0); }
static irqreturn_t diva_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val, sval; u_long flags; int cnt=5; spin_lock_irqsave(&cs->lock, flags); while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) { val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40); if (val) hscx_int_main(cs, val); val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA); if (val) isac_interrupt(cs, val); cnt--; } if (!cnt) printk(KERN_WARNING "Diva: IRQ LOOP\n"); writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF); writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF); writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF); writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0); writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0); writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static irqreturn_t sportster_interrupt(int intno, void *dev_id) { struct IsdnCardState *cs = dev_id; u_char val; u_long flags; spin_lock_irqsave(&cs->lock, flags); val = READHSCX(cs, 1, HSCX_ISTA); Start_HSCX: if (val) hscx_int_main(cs, val); val = ReadISAC(cs, ISAC_ISTA); Start_ISAC: if (val) isac_interrupt(cs, val); val = READHSCX(cs, 1, HSCX_ISTA); if (val) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = ReadISAC(cs, ISAC_ISTA); if (val) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } /* get a new irq impulse if there any pending */ bytein(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ +1); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static irqreturn_t avm_a1p_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val, sval; u_long flags; spin_lock_irqsave(&cs->lock, flags); while ((sval = (~bytein(cs->hw.avm.cfg_reg+ASL0_OFFSET) & ASL0_R_IRQPENDING))) { if (cs->debug & L1_DEB_INTSTAT) debugl1(cs, "avm IntStatus %x", sval); if (sval & ASL0_R_HSCX) { val = ReadHSCX(cs, 1, HSCX_ISTA); if (val) hscx_int_main(cs, val); } if (sval & ASL0_R_ISAC) { val = ReadISAC(cs, ISAC_ISTA); if (val) isac_interrupt(cs, val); } } WriteHSCX(cs, 0, HSCX_MASK, 0xff); WriteHSCX(cs, 1, HSCX_MASK, 0xff); WriteISAC(cs, ISAC_MASK, 0xff); WriteISAC(cs, ISAC_MASK, 0x00); WriteHSCX(cs, 0, HSCX_MASK, 0x00); WriteHSCX(cs, 1, HSCX_MASK, 0x00); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static irqreturn_t gazel_interrupt(int intno, void *dev_id, struct pt_regs *regs) { #define MAXCOUNT 5 struct IsdnCardState *cs = dev_id; u_char valisac, valhscx; int count = 0; u_long flags; spin_lock_irqsave(&cs->lock, flags); do { valhscx = ReadHSCX(cs, 1, HSCX_ISTA); if (valhscx) hscx_int_main(cs, valhscx); valisac = ReadISAC(cs, ISAC_ISTA); if (valisac) isac_interrupt(cs, valisac); count++; } while ((valhscx || valisac) && (count < MAXCOUNT)); WriteHSCX(cs, 0, HSCX_MASK, 0xFF); WriteHSCX(cs, 1, HSCX_MASK, 0xFF); WriteISAC(cs, ISAC_MASK, 0xFF); WriteISAC(cs, ISAC_MASK, 0x0); WriteHSCX(cs, 0, HSCX_MASK, 0x0); WriteHSCX(cs, 1, HSCX_MASK, 0x0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static void elsa_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char ista,val; int icnt=5; if (!cs) { printk(KERN_WARNING "Elsa: Spurious interrupt!\n"); return; } if (cs->subtyp == ELSA_QS1000PCI || cs->subtyp == ELSA_QS3000PCI) { val = bytein(cs->hw.elsa.cfg + 0x4c); /* PCI IRQ */ if (!(val & ELSA_PCI_IRQ_MASK)) return; } #if ARCOFI_USE if (cs->hw.elsa.MFlag) { val = serial_inp(cs, UART_IIR); if (!(val & UART_IIR_NO_INT)) { debugl1(cs,"IIR %02x", val); rs_interrupt_elsa(intno, cs); } } #endif ista = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ISTA); Start_IPAC: if (cs->debug & L1_DEB_IPAC) debugl1(cs, "IPAC ISTA %02X", ista); if (ista & 0x0f) { val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); if (ista & 0x01) val |= 0x01; if (ista & 0x04) val |= 0x02; if (ista & 0x08) val |= 0x04; if (val) hscx_int_main(cs, val); } if (ista & 0x20) { val = 0xfe & readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA + 0x80); if (val) { isac_interrupt(cs, val); } } if (ista & 0x10) { val = 0x01; isac_interrupt(cs, val); } ista = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ISTA); if ((ista & 0x3f) && icnt) { icnt--; goto Start_IPAC; } if (!icnt) printk(KERN_WARNING "ELSA IRQ LOOP\n"); writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_MASK, 0xFF); writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_MASK, 0xC0); }
static irqreturn_t telespci_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char hval, ival; u_long flags; spin_lock_irqsave(&cs->lock, flags); hval = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); if (hval) hscx_int_main(cs, hval); ival = readisac(cs->hw.teles0.membase, ISAC_ISTA); if ((hval | ival) == 0) { spin_unlock_irqrestore(&cs->lock, flags); return IRQ_NONE; } if (ival) isac_interrupt(cs, ival); /* Clear interrupt register for Zoran PCI controller */ writel(0x70000000, cs->hw.teles0.membase + 0x3C); writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF); writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0); writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static void avm_a1_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val, sval; if (!cs) { printk(KERN_WARNING "AVM A1: Spurious interrupt!\n"); return; } while (((sval = bytein(cs->hw.avm.cfg_reg)) & 0xf) != 0x7) { if (!(sval & AVM_A1_STAT_TIMER)) { byteout(cs->hw.avm.cfg_reg, 0x1E); sval = bytein(cs->hw.avm.cfg_reg); } else if (cs->debug & L1_DEB_INTSTAT) debugl1(cs, "avm IntStatus %x", sval); if (!(sval & AVM_A1_STAT_HSCX)) { val = readreg(cs->hw.avm.hscx[1], HSCX_ISTA); if (val) hscx_int_main(cs, val); } if (!(sval & AVM_A1_STAT_ISAC)) { val = readreg(cs->hw.avm.isac, ISAC_ISTA); if (val) isac_interrupt(cs, val); } } writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); writereg(cs->hw.avm.isac, ISAC_MASK, 0xFF); writereg(cs->hw.avm.isac, ISAC_MASK, 0x0); writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0x0); }
static void diva_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val, sval; int cnt=5; if (!cs) { printk(KERN_WARNING "Diva: Spurious interrupt!\n"); return; } while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) { val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40); if (val) hscx_int_main(cs, val); val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA); if (val) isac_interrupt(cs, val); cnt--; } if (!cnt) printk(KERN_WARNING "Diva: IRQ LOOP\n"); writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF); writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF); writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF); writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0); writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0); writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0); }
static void telespci_interrupt(int intno, void *dev_id, struct pt_regs *regs) { #define MAXCOUNT 20 struct IsdnCardState *cs = dev_id; u_char val; if (!cs) { printk(KERN_WARNING "TelesPCI: Spurious interrupt!\n"); return; } val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); if (val) hscx_int_main(cs, val); val = readisac(cs->hw.teles0.membase, ISAC_ISTA); if (val) isac_interrupt(cs, val); /* Clear interrupt register for Zoran PCI controller */ writel(0x70000000, cs->hw.teles0.membase + 0x3C); writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF); writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0); writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); }
static irqreturn_t avm_a1_interrupt(int intno, void *dev_id) { struct IsdnCardState *cs = dev_id; u_char val, sval; u_long flags; spin_lock_irqsave(&cs->lock, flags); while (((sval = bytein(cs->hw.avm.cfg_reg)) & 0xf) != 0x7) { if (!(sval & AVM_A1_STAT_TIMER)) { byteout(cs->hw.avm.cfg_reg, 0x1E); sval = bytein(cs->hw.avm.cfg_reg); } else if (cs->debug & L1_DEB_INTSTAT) debugl1(cs, "avm IntStatus %x", sval); if (!(sval & AVM_A1_STAT_HSCX)) { val = readreg(cs->hw.avm.hscx[1], HSCX_ISTA); if (val) hscx_int_main(cs, val); } if (!(sval & AVM_A1_STAT_ISAC)) { val = readreg(cs->hw.avm.isac, ISAC_ISTA); if (val) isac_interrupt(cs, val); } } writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); writereg(cs->hw.avm.isac, ISAC_MASK, 0xFF); writereg(cs->hw.avm.isac, ISAC_MASK, 0x0); writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0x0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static void niccy_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val, stat = 0; if (!cs) { printk(KERN_WARNING "Niccy: Spurious interrupt!\n"); return; } if (cs->subtyp == NICCY_PCI) { int ival; ival = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); if (!(ival & PCI_IRQ_ASSERT)) /* IRQ not for us (shared) */ return; outl(ival, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); } val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_ISTA + 0x40); Start_HSCX: if (val) { hscx_int_main(cs, val); stat |= 1; } val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA); Start_ISAC: if (val) { isac_interrupt(cs, val); stat |= 2; } val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_ISTA + 0x40); if (val) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA); if (val) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } if (stat & 1) { writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF); writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0xFF); writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0); writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0); } if (stat & 2) { writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0xFF); writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0); } }
static irqreturn_t bkm_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char ista, val, icnt = 5; u_long flags; spin_lock_irqsave(&cs->lock, flags); ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); if (!(ista & 0x3f)) { /* not this IPAC */ spin_unlock_irqrestore(&cs->lock, flags); return IRQ_NONE; } Start_IPAC: if (cs->debug & L1_DEB_IPAC) debugl1(cs, "IPAC ISTA %02X", ista); if (ista & 0x0f) { val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40); if (ista & 0x01) val |= 0x01; if (ista & 0x04) val |= 0x02; if (ista & 0x08) val |= 0x04; if (val) { hscx_int_main(cs, val); } } if (ista & 0x20) { val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80); if (val) { isac_interrupt(cs, val); } } if (ista & 0x10) { val = 0x01; isac_interrupt(cs, val); } ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); if ((ista & 0x3f) && icnt) { icnt--; goto Start_IPAC; } if (!icnt) printk(KERN_WARNING "HiSax: %s (%s) IRQ LOOP\n", CardType[cs->typ], sct_quadro_subtypes[cs->subtyp]); writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF); writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static void bkm_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char ista, val, icnt = 5; if (!cs) { printk(KERN_WARNING "HiSax: Scitel Quadro: Spurious interrupt!\n"); return; } ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); if (!(ista & 0x3f)) /* not this IPAC */ return; Start_IPAC: if (cs->debug & L1_DEB_IPAC) debugl1(cs, "IPAC ISTA %02X", ista); if (ista & 0x0f) { val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40); if (ista & 0x01) val |= 0x01; if (ista & 0x04) val |= 0x02; if (ista & 0x08) val |= 0x04; if (val) { hscx_int_main(cs, val); } } if (ista & 0x20) { val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80); if (val) { isac_interrupt(cs, val); } } if (ista & 0x10) { val = 0x01; isac_interrupt(cs, val); } ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); if ((ista & 0x3f) && icnt) { icnt--; goto Start_IPAC; } if (!icnt) printk(KERN_WARNING "HiSax: %s (%s) IRQ LOOP\n", CardType[cs->typ], sct_quadro_subtypes[cs->subtyp]); writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF); writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0); }
static irqreturn_t niccy_interrupt(int intno, void *dev_id) { struct IsdnCardState *cs = dev_id; u_char val; u_long flags; spin_lock_irqsave(&cs->lock, flags); if (cs->subtyp == NICCY_PCI) { int ival; ival = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); if (!(ival & PCI_IRQ_ASSERT)) { /* IRQ not for us (shared) */ spin_unlock_irqrestore(&cs->lock, flags); return IRQ_NONE; } outl(ival, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); } val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_ISTA + 0x40); Start_HSCX: if (val) hscx_int_main(cs, val); val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA); Start_ISAC: if (val) isac_interrupt(cs, val); val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_ISTA + 0x40); if (val) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA); if (val) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF); writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0xFF); writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0xFF); writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0); writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0); writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40,0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static void teles0_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val, stat = 0; int count = 0; if (!cs) { printk(KERN_WARNING "Teles0: Spurious interrupt!\n"); return; } val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); Start_HSCX: if (val) { hscx_int_main(cs, val); stat |= 1; } val = readisac(cs->hw.teles0.membase, ISAC_ISTA); Start_ISAC: if (val) { isac_interrupt(cs, val); stat |= 2; } count++; val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); if (val && count < 20) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readisac(cs->hw.teles0.membase, ISAC_ISTA); if (val && count < 20) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } if (stat & 1) { writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); } if (stat & 2) { writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF); writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0); } }
static void sedlbauer_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char ista, val, icnt = 5; if (!cs) { printk(KERN_WARNING "Sedlbauer: Spurious interrupt!\n"); return; } ista = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ISTA); Start_IPAC: if (cs->debug & L1_DEB_IPAC) debugl1(cs, "IPAC ISTA %02X", ista); if (ista & 0x0f) { val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); if (ista & 0x01) val |= 0x01; if (ista & 0x04) val |= 0x02; if (ista & 0x08) val |= 0x04; if (val) hscx_int_main(cs, val); } if (ista & 0x20) { val = 0xfe & readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA | 0x80); if (val) { isac_interrupt(cs, val); } } if (ista & 0x10) { val = 0x01; isac_interrupt(cs, val); } ista = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ISTA); if ((ista & 0x3f) && icnt) { icnt--; goto Start_IPAC; } if (!icnt) if (cs->debug & L1_DEB_ISAC) debugl1(cs, "Sedlbauer IRQ LOOP"); writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xFF); writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xC0); }
static irqreturn_t sedlbauer_interrupt_ipac(int intno, void *dev_id) { struct IsdnCardState *cs = dev_id; u_char ista, val, icnt = 5; u_long flags; spin_lock_irqsave(&cs->lock, flags); ista = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ISTA); Start_IPAC: if (cs->debug & L1_DEB_IPAC) debugl1(cs, "IPAC ISTA %02X", ista); if (ista & 0x0f) { val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); if (ista & 0x01) val |= 0x01; if (ista & 0x04) val |= 0x02; if (ista & 0x08) val |= 0x04; if (val) hscx_int_main(cs, val); } if (ista & 0x20) { val = 0xfe & readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA | 0x80); if (val) { isac_interrupt(cs, val); } } if (ista & 0x10) { val = 0x01; isac_interrupt(cs, val); } ista = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ISTA); if ((ista & 0x3f) && icnt) { icnt--; goto Start_IPAC; } if (!icnt) if (cs->debug & L1_DEB_ISAC) debugl1(cs, "Sedlbauer IRQ LOOP"); writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xFF); writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xC0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static irqreturn_t diva_irq_ipac_isa(int intno, void *dev_id) { struct IsdnCardState *cs = dev_id; u_char ista, val; u_long flags; int icnt = 5; spin_lock_irqsave(&cs->lock, flags); ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA); Start_IPACISA: if (cs->debug & L1_DEB_IPAC) debugl1(cs, "IPAC ISTA %02X", ista); if (ista & 0x0f) { val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, HSCX_ISTA + 0x40); if (ista & 0x01) val |= 0x01; if (ista & 0x04) val |= 0x02; if (ista & 0x08) val |= 0x04; if (val) hscx_int_main(cs, val); } if (ista & 0x20) { val = 0xfe & readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA + 0x80); if (val) { isac_interrupt(cs, val); } } if (ista & 0x10) { val = 0x01; isac_interrupt(cs, val); } ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA); if ((ista & 0x3f) && icnt) { icnt--; goto Start_IPACISA; } if (!icnt) printk(KERN_WARNING "DIVA IPAC IRQ LOOP\n"); writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xFF); writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xC0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static irqreturn_t sedlbauer_interrupt(int intno, void *dev_id) { struct IsdnCardState *cs = dev_id; u_char val; u_long flags; spin_lock_irqsave(&cs->lock, flags); if ((cs->hw.sedl.bus == SEDL_BUS_PCMCIA) && (*cs->busy_flag == 1)) { /* The card tends to generate interrupts while being removed causing us to just crash the kernel. bad. */ spin_unlock_irqrestore(&cs->lock, flags); printk(KERN_WARNING "Sedlbauer: card not available!\n"); return IRQ_NONE; } val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); Start_HSCX: if (val) hscx_int_main(cs, val); val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); Start_ISAC: if (val) isac_interrupt(cs, val); val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); if (val) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); if (val) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF); writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF); writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF); writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0x0); writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0x0); writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0x0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static void sedlbauer_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val; if (!cs) { printk(KERN_WARNING "Sedlbauer: Spurious interrupt!\n"); return; } if ((cs->hw.sedl.bus == SEDL_BUS_PCMCIA) && (*cs->busy_flag == 1)) { /* The card tends to generate interrupts while being removed causing us to just crash the kernel. bad. */ printk(KERN_WARNING "Sedlbauer: card not available!\n"); return; } val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); Start_HSCX: if (val) hscx_int_main(cs, val); val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); Start_ISAC: if (val) isac_interrupt(cs, val); val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); if (val) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); if (val) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF); writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF); writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF); writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0x0); writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0x0); writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0x0); }
static void ix1micro_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val, stat = 0; if (!cs) { printk(KERN_WARNING "IX1: Spurious interrupt!\n"); return; } val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); Start_HSCX: if (val) { hscx_int_main(cs, val); stat |= 1; } val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA); Start_ISAC: if (val) { isac_interrupt(cs, val); stat |= 2; } val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); if (val) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA); if (val) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } if (stat & 1) { writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0); } if (stat & 2) { writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF); writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0); } }
static void saphir_interrupt(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char val; if (!cs) { printk(KERN_WARNING "saphir: Spurious interrupt!\n"); return; } val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); Start_HSCX: if (val) hscx_int_main(cs, val); val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA); Start_ISAC: if (val) isac_interrupt(cs, val); val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); if (val) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA); if (val) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } /* Watchdog */ if (cs->hw.saphir.timer.function) { del_timer(&cs->hw.saphir.timer); cs->hw.saphir.timer.expires = jiffies + 1*HZ; add_timer(&cs->hw.saphir.timer); } else printk(KERN_WARNING "saphir: Spurious timer!\n"); writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF); writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF); writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0xFF); writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0); writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0); writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0); }
static void gazel_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs) { struct IsdnCardState *cs = dev_id; u_char ista, val; int count = 0; if (!cs) { printk(KERN_WARNING "Gazel: Spurious interrupt!\n"); return; } ista = ReadISAC(cs, IPAC_ISTA - 0x80); do { if (ista & 0x0f) { val = ReadHSCX(cs, 1, HSCX_ISTA); if (ista & 0x01) val |= 0x01; if (ista & 0x04) val |= 0x02; if (ista & 0x08) val |= 0x04; if (val) { hscx_int_main(cs, val); } } if (ista & 0x20) { val = 0xfe & ReadISAC(cs, ISAC_ISTA); if (val) { isac_interrupt(cs, val); } } if (ista & 0x10) { val = 0x01; isac_interrupt(cs, val); } ista = ReadISAC(cs, IPAC_ISTA - 0x80); count++; } while ((ista & 0x3f) && (count < MAXCOUNT)); WriteISAC(cs, IPAC_MASK - 0x80, 0xFF); WriteISAC(cs, IPAC_MASK - 0x80, 0xC0); }
static irqreturn_t gazel_interrupt_ipac(int intno, void *dev_id) { struct IsdnCardState *cs = dev_id; u_char ista, val; int count = 0; u_long flags; spin_lock_irqsave(&cs->lock, flags); ista = ReadISAC(cs, IPAC_ISTA - 0x80); do { if (ista & 0x0f) { val = ReadHSCX(cs, 1, HSCX_ISTA); if (ista & 0x01) val |= 0x01; if (ista & 0x04) val |= 0x02; if (ista & 0x08) val |= 0x04; if (val) { hscx_int_main(cs, val); } } if (ista & 0x20) { val = 0xfe & ReadISAC(cs, ISAC_ISTA); if (val) { isac_interrupt(cs, val); } } if (ista & 0x10) { val = 0x01; isac_interrupt(cs, val); } ista = ReadISAC(cs, IPAC_ISTA - 0x80); count++; } while ((ista & 0x3f) && (count < MAXCOUNT)); WriteISAC(cs, IPAC_MASK - 0x80, 0xFF); WriteISAC(cs, IPAC_MASK - 0x80, 0xC0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static irqreturn_t teles3_interrupt(int intno, void *dev_id, struct pt_regs *regs) { #define MAXCOUNT 5 struct IsdnCardState *cs = dev_id; u_char val; u_long flags; int count = 0; spin_lock_irqsave(&cs->lock, flags); val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); Start_HSCX: if (val) hscx_int_main(cs, val); val = readreg(cs->hw.teles3.isac, ISAC_ISTA); Start_ISAC: if (val) isac_interrupt(cs, val); count++; val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); if (val && count < MAXCOUNT) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readreg(cs->hw.teles3.isac, ISAC_ISTA); if (val && count < MAXCOUNT) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } if (count >= MAXCOUNT) printk(KERN_WARNING "Teles3: more than %d loops in teles3_interrupt\n", count); writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); writereg(cs->hw.teles3.isac, ISAC_MASK, 0xFF); writereg(cs->hw.teles3.isac, ISAC_MASK, 0x0); writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }
static void teles3_interrupt(int intno, void *dev_id, struct pt_regs *regs) { #define MAXCOUNT 5 struct IsdnCardState *cs = dev_id; u_char val; int count = 0; if (!cs) { printk(KERN_WARNING "Teles: Spurious interrupt!\n"); return; } val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); Start_HSCX: if (val) hscx_int_main(cs, val); val = readreg(cs->hw.teles3.isac, ISAC_ISTA); Start_ISAC: if (val) isac_interrupt(cs, val); count++; val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); if (val && count < MAXCOUNT) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readreg(cs->hw.teles3.isac, ISAC_ISTA); if (val && count < MAXCOUNT) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } if (count >= MAXCOUNT) printk(KERN_WARNING "Teles3: more than %d loops in teles3_interrupt\n", count); writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); writereg(cs->hw.teles3.isac, ISAC_MASK, 0xFF); writereg(cs->hw.teles3.isac, ISAC_MASK, 0x0); writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); }
static irqreturn_t saphir_interrupt(int intno, void *dev_id) { struct IsdnCardState *cs = dev_id; u_char val; u_long flags; spin_lock_irqsave(&cs->lock, flags); val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); Start_HSCX: if (val) hscx_int_main(cs, val); val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA); Start_ISAC: if (val) isac_interrupt(cs, val); val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); if (val) { if (cs->debug & L1_DEB_HSCX) debugl1(cs, "HSCX IntStat after IntRoutine"); goto Start_HSCX; } val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA); if (val) { if (cs->debug & L1_DEB_ISAC) debugl1(cs, "ISAC IntStat after IntRoutine"); goto Start_ISAC; } /* Watchdog */ if (cs->hw.saphir.timer.function) mod_timer(&cs->hw.saphir.timer, jiffies+1*HZ); else printk(KERN_WARNING "saphir: Spurious timer!\n"); writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF); writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF); writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0xFF); writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0); writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0); writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0); spin_unlock_irqrestore(&cs->lock, flags); return IRQ_HANDLED; }