/** * hsi_driver_cancel_write_interrupt - Cancel pending write interrupt. * @dev - hsi device channel where to cancel the pending interrupt. * * Return: -ECANCELED : write cancel success, data not transfered to TX FIFO * 0 : transfer is already over, data already transfered to TX FIFO * * Note: whatever returned value, write callback will not be called after * write cancel. */ int hsi_driver_cancel_write_interrupt(struct hsi_channel *ch) { struct hsi_port *p = ch->hsi_port; unsigned int port = p->port_number; unsigned int channel = ch->channel_number; void __iomem *base = p->hsi_controller->base; u32 status_reg; long buff_offset; status_reg = hsi_inl(base, HSI_SYS_MPU_ENABLE_CH_REG(port, p->n_irq, channel)); if (!(status_reg & HSI_HST_DATAACCEPT(channel))) { dev_dbg(&ch->dev->device, "Write cancel on not " "enabled channel %d ENABLE REG 0x%08X", channel, status_reg); } status_reg &= hsi_inl(base, HSI_SYS_MPU_STATUS_CH_REG(port, p->n_irq, channel)); hsi_outl_and(~HSI_HST_DATAACCEPT(channel), base, HSI_SYS_MPU_ENABLE_CH_REG(port, p->n_irq, channel)); buff_offset = hsi_hst_bufstate_f_reg(p->hsi_controller, port, channel); if (buff_offset >= 0) hsi_outl_and(~HSI_BUFSTATE_CHANNEL(channel), base, buff_offset); hsi_reset_ch_write(ch); return status_reg & HSI_HST_DATAACCEPT(channel) ? 0 : -ECANCELED; }
/** * hsi_driver_cancel_write_dma - Cancel an ongoing GDD [DMA] write for the * specified hsi channel. * @hsi_ch - pointer to the hsi_channel to cancel DMA write. * * hsi_controller lock must be held before calling this function. * * Return: -ENXIO : No DMA channel found for specified HSI channel * -ECANCELED : DMA cancel success, data not transfered to TX FIFO * 0 : DMA transfer is already over, data already transfered to TX FIFO * * Note: whatever returned value, write callback will not be called after * write cancel. */ int hsi_driver_cancel_write_dma(struct hsi_channel *hsi_ch) { int lch = hsi_ch->write_data.lch; unsigned int port = hsi_ch->hsi_port->port_number; unsigned int channel = hsi_ch->channel_number; struct hsi_dev *hsi_ctrl = hsi_ch->hsi_port->hsi_controller; u16 ccr, gdd_csr; long buff_offset; u32 status_reg; dma_addr_t dma_h; size_t size; if (lch < 0) { dev_err(&hsi_ch->dev->device, "No DMA channel found for HSI " "channel %d\n", hsi_ch->channel_number); return -ENXIO; } ccr = hsi_inw(hsi_ctrl->base, HSI_GDD_CCR_REG(lch)); if (!(ccr & HSI_CCR_ENABLE)) { dev_dbg(&hsi_ch->dev->device, "Write cancel on not " "enabled logical channel %d CCR REG 0x%04X\n", lch, ccr); } status_reg = hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_STATUS_REG); status_reg &= hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG); hsi_outw_and(~HSI_CCR_ENABLE, hsi_ctrl->base, HSI_GDD_CCR_REG(lch)); /* Clear CSR register by reading it, as it is cleared automaticaly */ /* by HW after SW read. */ gdd_csr = hsi_inw(hsi_ctrl->base, HSI_GDD_CSR_REG(lch)); hsi_outl_and(~HSI_GDD_LCH(lch), hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG); hsi_outl(HSI_GDD_LCH(lch), hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_STATUS_REG); /* Unmap DMA region */ dma_h = hsi_inl(hsi_ctrl->base, HSI_GDD_CSSA_REG(lch)); size = hsi_inw(hsi_ctrl->base, HSI_GDD_CEN_REG(lch)) * 4; dma_unmap_single(hsi_ctrl->dev, dma_h, size, DMA_TO_DEVICE); buff_offset = hsi_hst_bufstate_f_reg(hsi_ctrl, port, channel); if (buff_offset >= 0) hsi_outl_and(~HSI_BUFSTATE_CHANNEL(channel), hsi_ctrl->base, buff_offset); hsi_reset_ch_write(hsi_ch); return status_reg & HSI_GDD_LCH(lch) ? 0 : -ECANCELED; }
/* Disables the CAWAKE, BREAK, or ERROR interrupt for the given port */ int hsi_driver_disable_interrupt(struct hsi_port *pport, u32 flag) { hsi_outl_and(~flag, pport->hsi_controller->base, HSI_SYS_MPU_ENABLE_REG(pport->port_number, pport->n_irq)); return 0; }
/** * hsi_runtime_suspend - Prepare HSI for low power : device will not process data and will not communicate with the CPU * @dev - reference to the hsi device. * * Return value : -EBUSY or -EAGAIN if device is busy and still operational * */ int hsi_runtime_suspend(struct device *dev) { struct platform_device *pd = to_platform_device(dev); struct hsi_dev *hsi_ctrl = platform_get_drvdata(pd); struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data; int port; dev_dbg(dev, "%s\n", __func__); if (!hsi_ctrl->clock_enabled) dev_warn(dev, "Warning: clock status mismatch vs runtime PM\n"); /* Save context */ hsi_save_ctx(hsi_ctrl); hsi_ctrl->clock_enabled = false; /* Put HSR into SLEEP mode to force ACREADY to low while HSI is idle */ for (port = 1; port <= pdata->num_ports; port++) { hsi_outl_and(HSI_HSR_MODE_MODE_VAL_SLEEP, hsi_ctrl->base, HSI_HSR_MODE_REG(port)); } /* HSI is going to INA/RET/OFF, it needs IO wakeup mechanism enabled */ if (device_may_wakeup(dev)) pdata->wakeup_enable(0); else pdata->wakeup_disable(0); /* HSI is now ready to be put in low power state */ return 0; }
static void do_channel_tx(struct hsi_channel *ch) { struct hsi_dev *hsi_ctrl = ch->hsi_port->hsi_controller; void __iomem *base = hsi_ctrl->base; unsigned int n_ch; unsigned int n_p; unsigned int irq; long buff_offset; n_ch = ch->channel_number; n_p = ch->hsi_port->port_number; irq = ch->hsi_port->n_irq; spin_lock(&hsi_ctrl->lock); if (ch->write_data.addr == NULL) { hsi_outl_and(~HSI_HST_DATAACCEPT(n_ch), base, HSI_SYS_MPU_ENABLE_CH_REG(n_p, irq, n_ch)); hsi_reset_ch_write(ch); spin_unlock(&hsi_ctrl->lock); (*ch->write_done)(ch->dev, 1); } else { buff_offset = hsi_hst_buffer_reg(hsi_ctrl, n_p, n_ch); if (buff_offset >= 0) { hsi_outl(*(ch->write_data.addr), base, buff_offset); ch->write_data.addr = NULL; } spin_unlock(&hsi_ctrl->lock); } }
/** * hsi_softreset - Force a SW RESET of HSI (core + DMA) * * @hsi_ctrl - reference to the hsi controller to be reset. * */ int hsi_softreset(struct hsi_dev *hsi_ctrl) { unsigned int ind = 0; unsigned int port; void __iomem *base = hsi_ctrl->base; u32 status; /* HSI-C1BUG00088: i696 : HSI: Issue with SW reset * No recovery from SW reset under specific circumstances * If a SW RESET is done while some HSI errors are still not * acknowledged, the HSR FSM is stucked. */ if (is_hsi_errata(hsi_ctrl, HSI_ERRATUM_i696_SW_RESET_FSM_STUCK)) { for (port = 1; port <= hsi_ctrl->max_p; port++) { hsi_outl_and(HSI_HSR_MODE_MODE_VAL_SLEEP, base, HSI_HSR_MODE_REG(port)); hsi_outl(HSI_HSR_ERROR_ALL, base, HSI_HSR_ERRORACK_REG(port)); } } /* Reseting HSI Block */ hsi_outl_or(HSI_SOFTRESET, base, HSI_SYS_SYSCONFIG_REG); do { status = hsi_inl(base, HSI_SYS_SYSSTATUS_REG); ind++; } while ((!(status & HSI_RESETDONE)) && (ind < HSI_RESETDONE_MAX_RETRIES)); if (ind >= HSI_RESETDONE_MAX_RETRIES) { dev_err(hsi_ctrl->dev, "HSI SW_RESET failed to complete within" " %d retries.\n", HSI_RESETDONE_MAX_RETRIES); return -EIO; } else if (ind > HSI_RESETDONE_NORMAL_RETRIES) { dev_warn(hsi_ctrl->dev, "HSI SW_RESET abnormally long:" " %d retries to complete.\n", ind); } ind = 0; /* Reseting DMA Engine */ hsi_outl_or(HSI_GDD_GRST_SWRESET, base, HSI_GDD_GRST_REG); do { status = hsi_inl(base, HSI_GDD_GRST_REG); ind++; } while ((status & HSI_GDD_GRST_SWRESET) && (ind < HSI_RESETDONE_MAX_RETRIES)); if (ind >= HSI_RESETDONE_MAX_RETRIES) { dev_err(hsi_ctrl->dev, "HSI DMA SW_RESET failed to complete" " within %d retries.\n", HSI_RESETDONE_MAX_RETRIES); return -EIO; } if (ind > HSI_RESETDONE_NORMAL_RETRIES) { dev_warn(hsi_ctrl->dev, "HSI DMA SW_RESET abnormally long:" " %d retries to complete.\n", ind); } return 0; }
void hsi_driver_disable_read_interrupt(struct hsi_channel *ch) { struct hsi_port *p = ch->hsi_port; unsigned int port = p->port_number; unsigned int channel = ch->channel_number; void __iomem *base = p->hsi_controller->base; hsi_outl_and(~HSI_HSR_DATAAVAILABLE(channel), base, HSI_SYS_MPU_ENABLE_CH_REG(port, p->n_irq, channel)); }
/** * hsi_softreset - Force a SW RESET of HSI (core + DMA) * * @hsi_ctrl - reference to the hsi controller to be reset. * */ int hsi_softreset(struct hsi_dev *hsi_ctrl) { unsigned int ind = 0; unsigned int port; void __iomem *base = hsi_ctrl->base; u32 status; /* SW WA for HSI-C1BUG00088 OMAP4430 HSI : No recovery from SW reset */ /* under specific circumstances */ for (port = 1; port <= hsi_ctrl->max_p; port++) { hsi_outl_and(HSI_HSR_MODE_MODE_VAL_SLEEP, base, HSI_HSR_MODE_REG(port)); hsi_outl(HSI_HSR_ERROR_ALL, base, HSI_HSR_ERRORACK_REG(port)); } /* Reseting HSI Block */ hsi_outl_or(HSI_SOFTRESET, base, HSI_SYS_SYSCONFIG_REG); do { status = hsi_inl(base, HSI_SYS_SYSSTATUS_REG); ind++; } while ((!(status & HSI_RESETDONE)) && (ind < HSI_RESETDONE_MAX_RETRIES)); if (ind >= HSI_RESETDONE_MAX_RETRIES) { dev_err(hsi_ctrl->dev, "HSI SW_RESET failed to complete within" " %d retries.\n", HSI_RESETDONE_MAX_RETRIES); return -EIO; } else if (ind > HSI_RESETDONE_NORMAL_RETRIES) { dev_warn(hsi_ctrl->dev, "HSI SW_RESET abnormally long:" " %d retries to complete.\n", ind); } ind = 0; /* Reseting DMA Engine */ hsi_outl_or(HSI_GDD_GRST_SWRESET, base, HSI_GDD_GRST_REG); do { status = hsi_inl(base, HSI_GDD_GRST_REG); ind++; } while ((status & HSI_GDD_GRST_SWRESET) && (ind < HSI_RESETDONE_MAX_RETRIES)); if (ind >= HSI_RESETDONE_MAX_RETRIES) { dev_err(hsi_ctrl->dev, "HSI DMA SW_RESET failed to complete" " within %d retries.\n", HSI_RESETDONE_MAX_RETRIES); return -EIO; } if (ind > HSI_RESETDONE_NORMAL_RETRIES) { dev_warn(hsi_ctrl->dev, "HSI DMA SW_RESET abnormally long:" " %d retries to complete.\n", ind); } return 0; }
void hsi_hsr_suspend(struct hsi_dev *hsi_ctrl) { struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data; int port; dev_dbg(hsi_ctrl->dev, "%s\n", __func__); for (port = 1; port <= pdata->num_ports; port++) { hsi_outl_and(HSI_HSR_MODE_MODE_VAL_SLEEP, hsi_ctrl->base, HSI_HSR_MODE_REG(port)); } }
void hsi_hsr_suspend(struct hsi_dev *hsi_ctrl) { struct hsi_platform_data *pdata = hsi_ctrl->dev->platform_data; int port; dev_dbg(hsi_ctrl->dev, "%s\n", __func__); /* Put HSR into SLEEP mode to force ACREADY to low while HSI is idle */ for (port = 1; port <= pdata->num_ports; port++) { hsi_outl_and(HSI_HSR_MODE_MODE_VAL_SLEEP, hsi_ctrl->base, HSI_HSR_MODE_REG(port)); } }
/** * hsi_driver_cancel_read_dma - Cancel an ongoing GDD [DMA] read for the * specified hsi channel. * @hsi_ch - pointer to the hsi_channel to cancel DMA read. * * hsi_controller lock must be held before calling this function. * * Return: -ENXIO : No DMA channel found for specified HSI channel * -ECANCELED : DMA cancel success, data not available at expected * address. * 0 : DMA transfer is already over, data already available at * expected address. * * Note: whatever returned value, read callback will not be called after cancel. */ int hsi_driver_cancel_read_dma(struct hsi_channel *hsi_ch) { int lch = hsi_ch->read_data.lch; struct hsi_dev *hsi_ctrl = hsi_ch->hsi_port->hsi_controller; u16 ccr, gdd_csr; u32 status_reg; dma_addr_t dma_h; size_t size; /* Re-enable interrupts for polling if needed */ if (hsi_ch->flags & HSI_CH_RX_POLL) hsi_driver_enable_read_interrupt(hsi_ch, NULL); if (lch < 0) { dev_err(&hsi_ch->dev->device, "No DMA channel found for HSI " "channel %d\n", hsi_ch->channel_number); return -ENXIO; } ccr = hsi_inw(hsi_ctrl->base, HSI_GDD_CCR_REG(lch)); if (!(ccr & HSI_CCR_ENABLE)) { dev_dbg(&hsi_ch->dev->device, "Read cancel on not " "enabled logical channel %d CCR REG 0x%04X\n", lch, ccr); } status_reg = hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_STATUS_REG); status_reg &= hsi_inl(hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG); hsi_outw_and(~HSI_CCR_ENABLE, hsi_ctrl->base, HSI_GDD_CCR_REG(lch)); /* Clear CSR register by reading it, as it is cleared automaticaly */ /* by HW after SW read */ gdd_csr = hsi_inw(hsi_ctrl->base, HSI_GDD_CSR_REG(lch)); hsi_outl_and(~HSI_GDD_LCH(lch), hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG); hsi_outl(HSI_GDD_LCH(lch), hsi_ctrl->base, HSI_SYS_GDD_MPU_IRQ_STATUS_REG); /* Unmap DMA region - Access to the buffer is now safe */ dma_h = hsi_inl(hsi_ctrl->base, HSI_GDD_CDSA_REG(lch)); size = hsi_inw(hsi_ctrl->base, HSI_GDD_CEN_REG(lch)) * 4; dma_unmap_single(hsi_ctrl->dev, dma_h, size, DMA_FROM_DEVICE); hsi_reset_ch_read(hsi_ch); return status_reg & HSI_GDD_LCH(lch) ? 0 : -ECANCELED; }
static void do_channel_rx(struct hsi_channel *ch) { struct hsi_dev *hsi_ctrl = ch->hsi_port->hsi_controller; void __iomem *base = ch->hsi_port->hsi_controller->base; unsigned int n_ch; unsigned int n_p; unsigned int irq; long buff_offset; int rx_poll = 0; int data_read = 0; n_ch = ch->channel_number; n_p = ch->hsi_port->port_number; irq = ch->hsi_port->n_irq; spin_lock(&hsi_ctrl->lock); if (ch->flags & HSI_CH_RX_POLL) rx_poll = 1; if (ch->read_data.addr) { buff_offset = hsi_hsr_buffer_reg(hsi_ctrl, n_p, n_ch); if (buff_offset >= 0) { data_read = 1; *(ch->read_data.addr) = hsi_inl(base, buff_offset); } } hsi_outl_and(~HSI_HSR_DATAAVAILABLE(n_ch), base, HSI_SYS_MPU_ENABLE_CH_REG(n_p, irq, n_ch)); hsi_reset_ch_read(ch); spin_unlock(&hsi_ctrl->lock); if (rx_poll) hsi_port_event_handler(ch->hsi_port, HSI_EVENT_HSR_DATAAVAILABLE, (void *)n_ch); if (data_read) (*ch->read_done)(ch->dev, 1); }
/** * hsi_driver_cancel_read_interrupt - Cancel pending read interrupt. * @dev - hsi device channel where to cancel the pending interrupt. * * Return: -ECANCELED : read cancel success data not available at expected * address. * 0 : transfer is already over, data already available at expected * address. * * Note: whatever returned value, read callback will not be called after cancel. */ int hsi_driver_cancel_read_interrupt(struct hsi_channel *ch) { struct hsi_port *p = ch->hsi_port; unsigned int port = p->port_number; unsigned int channel = ch->channel_number; void __iomem *base = p->hsi_controller->base; u32 status_reg; status_reg = hsi_inl(base, HSI_SYS_MPU_ENABLE_CH_REG(port, p->n_irq, channel)); if (!(status_reg & HSI_HSR_DATAAVAILABLE(channel))) { dev_dbg(&ch->dev->device, "Read cancel on not " "enabled channel %d ENABLE REG 0x%08X", channel, status_reg); } status_reg &= hsi_inl(base, HSI_SYS_MPU_STATUS_CH_REG(port, p->n_irq, channel)); hsi_outl_and(~HSI_HSR_DATAAVAILABLE(channel), base, HSI_SYS_MPU_ENABLE_CH_REG(port, p->n_irq, channel)); hsi_reset_ch_read(ch); return status_reg & HSI_HSR_DATAAVAILABLE(channel) ? 0 : -ECANCELED; }
/** * hsi_ioctl - HSI I/O control * @dev - hsi device channel reference to apply the I/O control * (or port associated to it) * @command - HSI I/O control command * @arg - parameter associated to the control command. NULL, if no parameter. * * Return 0 on success, a negative value on failure. * */ int hsi_ioctl(struct hsi_device *dev, unsigned int command, void *arg) { struct hsi_channel *ch; struct hsi_dev *hsi_ctrl; struct hsi_port *pport; void __iomem *base; unsigned int port, channel; u32 acwake; int err = 0; int fifo = 0; u8 ret; struct hsi_platform_data *pdata; if (unlikely((!dev) || (!dev->ch) || (!dev->ch->hsi_port) || (!dev->ch->hsi_port->hsi_controller)) || (!(dev->ch->flags & HSI_CH_OPEN))) { pr_err(LOG_NAME "HSI IOCTL Invalid parameter\n"); return -EINVAL; } ch = dev->ch; pport = ch->hsi_port; hsi_ctrl = ch->hsi_port->hsi_controller; port = ch->hsi_port->port_number; channel = ch->channel_number; base = hsi_ctrl->base; dev_dbg(hsi_ctrl->dev, "IOCTL: ch %d, command %d\n", channel, command); spin_lock_bh(&hsi_ctrl->lock); hsi_clocks_enable_channel(hsi_ctrl->dev, channel, __func__); switch (command) { case HSI_IOCTL_ACWAKE_UP: /* Wake up request to Modem (typically OMAP initiated) */ /* Symetrical disable will be done in HSI_IOCTL_ACWAKE_DOWN */ if (ch->flags & HSI_CH_ACWAKE) { dev_dbg(hsi_ctrl->dev, "Duplicate ACWAKE UP\n"); err = -EPERM; goto out; } ch->flags |= HSI_CH_ACWAKE; pport->acwake_status |= BIT(channel); /* We only claim once the wake line per channel */ acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port)); if (!(acwake & HSI_WAKE(channel))) { hsi_outl(HSI_SET_WAKE(channel), base, HSI_SYS_SET_WAKE_REG(port)); } goto out; break; case HSI_IOCTL_ACWAKE_DOWN: /* Low power request initiation (OMAP initiated, typically */ /* following inactivity timeout) */ /* ACPU HSI block shall still be capable of receiving */ if (!(ch->flags & HSI_CH_ACWAKE)) { dev_dbg(hsi_ctrl->dev, "Duplicate ACWAKE DOWN\n"); err = -EPERM; goto out; } acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port)); if (unlikely(pport->acwake_status != (acwake & HSI_WAKE_MASK))) { dev_warn(hsi_ctrl->dev, "ACWAKE shadow register mismatch" " acwake_status: 0x%x, HSI_SYS_WAKE_REG: 0x%x", pport->acwake_status, acwake); pport->acwake_status = acwake & HSI_WAKE_MASK; } /* SSI_TODO: add safety check for SSI also */ ch->flags &= ~HSI_CH_ACWAKE; pport->acwake_status &= ~BIT(channel); /* Release the wake line per channel */ if ((acwake & HSI_WAKE(channel))) { hsi_outl(HSI_CLEAR_WAKE(channel), base, HSI_SYS_CLEAR_WAKE_REG(port)); } goto out; break; case HSI_IOCTL_SEND_BREAK: hsi_outl(1, base, HSI_HST_BREAK_REG(port)); /*HSI_TODO : need to deactivate clock after BREAK frames sent*/ /*Use interrupt ? (if TX BREAK INT exists)*/ break; case HSI_IOCTL_GET_ACWAKE: if (!arg) { err = -EINVAL; goto out; } *(u32 *)arg = hsi_inl(base, HSI_SYS_WAKE_REG(port)); break; case HSI_IOCTL_FLUSH_RX: ret = hsi_hsr_fifo_flush_channel(hsi_ctrl, port, channel); if (arg) *(size_t *)arg = ret; /* Ack the RX Int */ hsi_outl_and(~HSI_HSR_DATAAVAILABLE(channel), base, HSI_SYS_MPU_STATUS_CH_REG(port, pport->n_irq, channel)); break; case HSI_IOCTL_FLUSH_TX: ret = hsi_hst_fifo_flush_channel(hsi_ctrl, port, channel); if (arg) *(size_t *)arg = ret; /* Ack the TX Int */ hsi_outl_and(~HSI_HST_DATAACCEPT(channel), base, HSI_SYS_MPU_STATUS_CH_REG(port, pport->n_irq, channel)); break; case HSI_IOCTL_GET_CAWAKE: if (!arg) { err = -EINVAL; goto out; } err = hsi_get_cawake(dev->ch->hsi_port); if (err < 0) { err = -ENODEV; goto out; } *(u32 *)arg = err; break; case HSI_IOCTL_SET_RX: if (!arg) { err = -EINVAL; goto out; } err = hsi_set_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg); break; case HSI_IOCTL_GET_RX: if (!arg) { err = -EINVAL; goto out; } hsi_get_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg); break; case HSI_IOCTL_SET_TX: if (!arg) { err = -EINVAL; goto out; } err = hsi_set_tx(dev->ch->hsi_port, (struct hst_ctx *)arg); break; case HSI_IOCTL_GET_TX: if (!arg) { err = -EINVAL; goto out; } hsi_get_tx(dev->ch->hsi_port, (struct hst_ctx *)arg); break; case HSI_IOCTL_SW_RESET: dev_info(hsi_ctrl->dev, "SW Reset\n"); err = hsi_softreset(hsi_ctrl); /* Reset HSI config to default */ hsi_softreset_driver(hsi_ctrl); break; case HSI_IOCTL_GET_FIFO_OCCUPANCY: if (!arg) { err = -EINVAL; goto out; } fifo = hsi_fifo_get_id(hsi_ctrl, channel, port); if (unlikely(fifo < 0)) { dev_err(hsi_ctrl->dev, "No valid FIFO id found for " "channel %d.\n", channel); err = -EFAULT; goto out; } *(size_t *)arg = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo); break; case HSI_IOCTL_SET_WAKE_RX_3WIRES_MODE: dev_info(hsi_ctrl->dev, "Entering RX wakeup in 3 wires mode (no CAWAKE)\n"); pport->wake_rx_3_wires_mode = 1; /* HSI-C1BUG00085: ixxx: HSI wakeup issue in 3 wires mode * HSI will NOT generate the Swakeup for 2nd frame if it entered * IDLE after 1st received frame */ if (is_hsi_errata(hsi_ctrl, HSI_ERRATUM_ixxx_3WIRES_NO_SWAKEUP)) if (hsi_driver_device_is_hsi(to_platform_device (hsi_ctrl->dev))) hsi_set_pm_force_hsi_on(hsi_ctrl); /* When WAKE is not available, ACREADY must be set to 1 at * reset else remote will never have a chance to transmit. */ hsi_outl_or(HSI_SET_WAKE_3_WIRES | HSI_SET_WAKE_READY_LVL_1, base, HSI_SYS_SET_WAKE_REG(port)); hsi_driver_disable_interrupt(pport, HSI_CAWAKEDETECTED); break; case HSI_IOCTL_SET_WAKE_RX_4WIRES_MODE: dev_info(hsi_ctrl->dev, "Entering RX wakeup in 4 wires mode\n"); pport->wake_rx_3_wires_mode = 0; /* HSI-C1BUG00085: ixxx: HSI wakeup issue in 3 wires mode * HSI will NOT generate the Swakeup for 2nd frame if it entered * IDLE after 1st received frame */ if (is_hsi_errata(hsi_ctrl, HSI_ERRATUM_ixxx_3WIRES_NO_SWAKEUP)) if (hsi_driver_device_is_hsi(to_platform_device (hsi_ctrl->dev))) hsi_set_pm_default(hsi_ctrl); hsi_driver_enable_interrupt(pport, HSI_CAWAKEDETECTED); hsi_outl_and(HSI_SET_WAKE_3_WIRES_MASK, base, HSI_SYS_SET_WAKE_REG(port)); break; case HSI_IOCTL_SET_HI_SPEED: if (!arg) { err = -EINVAL; goto out; } hsi_ctrl->hsi_fclk_req = *(unsigned int *)arg ? HSI_FCLK_HI_SPEED : HSI_FCLK_LOW_SPEED; if (hsi_ctrl->hsi_fclk_req == hsi_ctrl->hsi_fclk_current) { dev_dbg(hsi_ctrl->dev, "HSI FClk already @%ldHz\n", hsi_ctrl->hsi_fclk_current); goto out; } if (hsi_is_controller_transfer_ongoing(hsi_ctrl)) { err = -EBUSY; goto out; } hsi_ctrl->clock_change_ongoing = true; spin_unlock_bh(&hsi_ctrl->lock); pdata = dev_get_platdata(hsi_ctrl->dev); /* Set the HSI FCLK to requested value. */ err = pdata->device_scale(hsi_ctrl->dev, hsi_ctrl->dev, hsi_ctrl->hsi_fclk_req); if (err < 0) { dev_err(hsi_ctrl->dev, "%s: Cannot set HSI FClk to" " %ldHz, err %d\n", __func__, hsi_ctrl->hsi_fclk_req, err); } else { dev_info(hsi_ctrl->dev, "HSI FClk changed from %ldHz to" " %ldHz\n", hsi_ctrl->hsi_fclk_current, hsi_ctrl->hsi_fclk_req); hsi_ctrl->hsi_fclk_current = hsi_ctrl->hsi_fclk_req; } spin_lock_bh(&hsi_ctrl->lock); hsi_ctrl->clock_change_ongoing = false; break; case HSI_IOCTL_GET_SPEED: if (!arg) { err = -EINVAL; goto out; } *(unsigned long *)arg = hsi_ctrl->hsi_fclk_current; break; default: err = -ENOIOCTLCMD; break; } out: /* All IOCTL end by disabling the clocks, except ACWAKE high. */ hsi_clocks_disable_channel(hsi_ctrl->dev, channel, __func__); spin_unlock_bh(&hsi_ctrl->lock); return err; }
/** * hsi_ioctl - HSI I/O control * @dev - hsi device channel reference to apply the I/O control * (or port associated to it) * @command - HSI I/O control command * @arg - parameter associated to the control command. NULL, if no parameter. * * Return 0 on success, a negative value on failure. * */ int hsi_ioctl(struct hsi_device *dev, unsigned int command, void *arg) { struct hsi_channel *ch; struct hsi_dev *hsi_ctrl; struct hsi_port *pport; void __iomem *base; unsigned int port, channel; u32 acwake; int err = 0, err_clk = 0; int fifo = 0; u8 ret; if (unlikely((!dev) || (!dev->ch) || (!dev->ch->hsi_port) || (!dev->ch->hsi_port->hsi_controller)) || (!(dev->ch->flags & HSI_CH_OPEN))) { pr_err(LOG_NAME "HSI IOCTL Invalid parameter\n"); return -EINVAL; } ch = dev->ch; pport = ch->hsi_port; hsi_ctrl = ch->hsi_port->hsi_controller; port = ch->hsi_port->port_number; channel = ch->channel_number; base = hsi_ctrl->base; dev_dbg(hsi_ctrl->dev, "IOCTL: ch %d, command %d\n", channel, command); spin_lock_bh(&hsi_ctrl->lock); err_clk = hsi_clocks_enable_channel(hsi_ctrl->dev, channel, __func__); if (err_clk < 0) { spin_unlock_bh(&hsi_ctrl->lock); return err_clk; } switch (command) { case HSI_IOCTL_ACWAKE_UP: /* Wake up request to Modem (typically OMAP initiated) */ /* Symetrical disable will be done in HSI_IOCTL_ACWAKE_DOWN */ if (ch->flags & HSI_CH_ACWAKE) { dev_dbg(hsi_ctrl->dev, "Duplicate ACWAKE UP\n"); err = -EPERM; goto out; } ch->flags |= HSI_CH_ACWAKE; pport->acwake_status |= BIT(channel); /* We only claim once the wake line per channel */ acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port)); if (!(acwake & HSI_WAKE(channel))) { hsi_outl(HSI_SET_WAKE(channel), base, HSI_SYS_SET_WAKE_REG(port)); } goto out; break; case HSI_IOCTL_ACWAKE_DOWN: /* Low power request initiation (OMAP initiated, typically */ /* following inactivity timeout) */ /* ACPU HSI block shall still be capable of receiving */ if (!(ch->flags & HSI_CH_ACWAKE)) { dev_dbg(hsi_ctrl->dev, "Duplicate ACWAKE DOWN\n"); err = -EPERM; goto out; } acwake = hsi_inl(base, HSI_SYS_WAKE_REG(port)); if (unlikely(pport->acwake_status != (acwake & HSI_WAKE_MASK))) { dev_warn(hsi_ctrl->dev, "ACWAKE shadow register mismatch" " acwake_status: 0x%x, HSI_SYS_WAKE_REG: 0x%x", pport->acwake_status, acwake); pport->acwake_status = acwake & HSI_WAKE_MASK; } /* SSI_TODO: add safety check for SSI also */ ch->flags &= ~HSI_CH_ACWAKE; pport->acwake_status &= ~BIT(channel); /* Release the wake line per channel */ if ((acwake & HSI_WAKE(channel))) { hsi_outl(HSI_CLEAR_WAKE(channel), base, HSI_SYS_CLEAR_WAKE_REG(port)); } goto out; break; case HSI_IOCTL_SEND_BREAK: hsi_outl(1, base, HSI_HST_BREAK_REG(port)); /*HSI_TODO : need to deactivate clock after BREAK frames sent*/ /*Use interrupt ? (if TX BREAK INT exists)*/ break; case HSI_IOCTL_GET_ACWAKE: if (!arg) { err = -EINVAL; goto out; } *(u32 *)arg = hsi_inl(base, HSI_SYS_WAKE_REG(port)); break; case HSI_IOCTL_FLUSH_RX: ret = hsi_hsr_fifo_flush_channel(hsi_ctrl, port, channel); if (arg) *(size_t *)arg = ret; /* Ack the RX Int */ hsi_outl_and(~HSI_HSR_DATAAVAILABLE(channel), base, HSI_SYS_MPU_STATUS_CH_REG(port, pport->n_irq, channel)); break; case HSI_IOCTL_FLUSH_TX: ret = hsi_hst_fifo_flush_channel(hsi_ctrl, port, channel); if (arg) *(size_t *)arg = ret; /* Ack the TX Int */ hsi_outl_and(~HSI_HST_DATAACCEPT(channel), base, HSI_SYS_MPU_STATUS_CH_REG(port, pport->n_irq, channel)); break; case HSI_IOCTL_GET_CAWAKE: if (!arg) { err = -EINVAL; goto out; } err = hsi_get_cawake(dev->ch->hsi_port); if (err < 0) { err = -ENODEV; goto out; } *(u32 *)arg = err; break; case HSI_IOCTL_SET_RX: if (!arg) { err = -EINVAL; goto out; } err = hsi_set_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg); break; case HSI_IOCTL_GET_RX: if (!arg) { err = -EINVAL; goto out; } hsi_get_rx(dev->ch->hsi_port, (struct hsr_ctx *)arg); break; case HSI_IOCTL_SET_TX: if (!arg) { err = -EINVAL; goto out; } err = hsi_set_tx(dev->ch->hsi_port, (struct hst_ctx *)arg); break; case HSI_IOCTL_GET_TX: if (!arg) { err = -EINVAL; goto out; } hsi_get_tx(dev->ch->hsi_port, (struct hst_ctx *)arg); break; case HSI_IOCTL_SW_RESET: dev_info(hsi_ctrl->dev, "SW Reset\n"); err = hsi_softreset(hsi_ctrl); /* Reset HSI config to default */ hsi_softreset_driver(hsi_ctrl); break; case HSI_IOCTL_GET_FIFO_OCCUPANCY: if (!arg) { err = -EINVAL; goto out; } fifo = hsi_fifo_get_id(hsi_ctrl, channel, port); if (unlikely(fifo < 0)) { dev_err(hsi_ctrl->dev, "No valid FIFO id found for " "channel %d.\n", channel); err = -EFAULT; goto out; } *(size_t *)arg = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo); break; default: err = -ENOIOCTLCMD; break; } out: /* All IOCTL end by disabling the clocks, except ACWAKE high. */ hsi_clocks_disable_channel(hsi_ctrl->dev, channel, __func__); spin_unlock_bh(&hsi_ctrl->lock); return err; }
static void do_hsi_gdd_lch(struct hsi_dev *hsi_ctrl, unsigned int gdd_lch) { void __iomem *base = hsi_ctrl->base; struct platform_device *pdev = to_platform_device(hsi_ctrl->dev); struct hsi_channel *ch; unsigned int port; unsigned int channel; unsigned int is_read_path; u32 gdd_csr; dma_addr_t dma_h; size_t size; int fifo, fifo_words_avail; if (hsi_get_info_from_gdd_lch(hsi_ctrl, gdd_lch, &port, &channel, &is_read_path) < 0) { dev_err(hsi_ctrl->dev, "Unable to match the DMA channel %d with" " an HSI channel\n", gdd_lch); return; } else { dev_dbg(hsi_ctrl->dev, "DMA event on gdd_lch=%d => port=%d, " "channel=%d, read=%d\n", gdd_lch, port, channel, is_read_path); } hsi_outl_and(~HSI_GDD_LCH(gdd_lch), base, HSI_SYS_GDD_MPU_IRQ_ENABLE_REG); /* Warning : CSR register is cleared automaticaly by HW after SW read */ gdd_csr = hsi_inw(base, HSI_GDD_CSR_REG(gdd_lch)); if (!(gdd_csr & HSI_CSR_TOUT)) { if (is_read_path) { /* Read path */ dma_h = hsi_inl(base, HSI_GDD_CDSA_REG(gdd_lch)); size = hsi_inw(base, HSI_GDD_CEN_REG(gdd_lch)) * 4; dma_sync_single_for_cpu(hsi_ctrl->dev, dma_h, size, DMA_FROM_DEVICE); dma_unmap_single(hsi_ctrl->dev, dma_h, size, DMA_FROM_DEVICE); ch = hsi_ctrl_get_ch(hsi_ctrl, port, channel); hsi_reset_ch_read(ch); dev_dbg(hsi_ctrl->dev, "Calling ch %d read callback " "(size %d).\n", channel, size/4); spin_unlock(&hsi_ctrl->lock); ch->read_done(ch->dev, size / 4); spin_lock(&hsi_ctrl->lock); /* Check if FIFO is correctly emptied */ if (hsi_driver_device_is_hsi(pdev)) { fifo = hsi_fifo_get_id(hsi_ctrl, channel, port); if (unlikely(fifo < 0)) { dev_err(hsi_ctrl->dev, "No valid FIFO " "id found for channel %d.\n", channel); return; } fifo_words_avail = hsi_get_rx_fifo_occupancy(hsi_ctrl, fifo); if (fifo_words_avail) dev_dbg(hsi_ctrl->dev, "FIFO %d not empty " "after DMA copy, remaining " "%d/%d frames\n", fifo, fifo_words_avail, HSI_HSR_FIFO_SIZE); } /* Re-enable interrupts for polling if needed */ if (ch->flags & HSI_CH_RX_POLL) hsi_driver_enable_read_interrupt(ch, NULL); } else { /* Write path */ dma_h = hsi_inl(base, HSI_GDD_CSSA_REG(gdd_lch)); size = hsi_inw(base, HSI_GDD_CEN_REG(gdd_lch)) * 4; dma_unmap_single(hsi_ctrl->dev, dma_h, size, DMA_TO_DEVICE); ch = hsi_ctrl_get_ch(hsi_ctrl, port, channel); hsi_reset_ch_write(ch); dev_dbg(hsi_ctrl->dev, "Calling ch %d write callback " "(size %d).\n", channel, size/4); spin_unlock(&hsi_ctrl->lock); ch->write_done(ch->dev, size / 4); spin_lock(&hsi_ctrl->lock); } } else { dev_err(hsi_ctrl->dev, "Time-out overflow Error on GDD transfer" " on gdd channel %d\n", gdd_lch); spin_unlock(&hsi_ctrl->lock); /* TODO : need to perform a DMA soft reset */ hsi_port_event_handler(&hsi_ctrl->hsi_port[port - 1], HSI_EVENT_ERROR, NULL); spin_lock(&hsi_ctrl->lock); } }