static void hsu_dma_stop_channel(struct hsu_dma_chan *hsuc) { unsigned long flags; spin_lock_irqsave(&hsuc->lock, flags); hsu_chan_disable(hsuc); hsu_chan_writel(hsuc, HSU_CH_DCR, 0); spin_unlock_irqrestore(&hsuc->lock, flags); }
static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc) { struct dma_slave_config *config = &hsuc->config; struct hsu_dma_desc *desc = hsuc->desc; u32 bsr = 0, mtsr = 0; /* to shut the compiler up */ u32 dcr = HSU_CH_DCR_CHSOE | HSU_CH_DCR_CHEI; unsigned int i, count; if (hsuc->direction == DMA_MEM_TO_DEV) { bsr = config->dst_maxburst; mtsr = config->dst_addr_width; } else if (hsuc->direction == DMA_DEV_TO_MEM) { bsr = config->src_maxburst; mtsr = config->src_addr_width; } hsu_chan_disable(hsuc); hsu_chan_writel(hsuc, HSU_CH_DCR, 0); hsu_chan_writel(hsuc, HSU_CH_BSR, bsr); hsu_chan_writel(hsuc, HSU_CH_MTSR, mtsr); /* Set descriptors */ count = (desc->nents - desc->active) % HSU_DMA_CHAN_NR_DESC; for (i = 0; i < count; i++) { hsu_chan_writel(hsuc, HSU_CH_DxSAR(i), desc->sg[i].addr); hsu_chan_writel(hsuc, HSU_CH_DxTSR(i), desc->sg[i].len); /* Prepare value for DCR */ dcr |= HSU_CH_DCR_DESCA(i); dcr |= HSU_CH_DCR_CHTOI(i); /* timeout bit, see HSU Errata 1 */ desc->active++; } /* Only for the last descriptor in the chain */ dcr |= HSU_CH_DCR_CHSOD(count - 1); dcr |= HSU_CH_DCR_CHDI(count - 1); hsu_chan_writel(hsuc, HSU_CH_DCR, dcr); hsu_chan_enable(hsuc); }
static void hsu_dma_stop_channel(struct hsu_dma_chan *hsuc) { hsu_chan_disable(hsuc); hsu_chan_writel(hsuc, HSU_CH_DCR, 0); }