void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been * replicated in every reference design since Parmer, so it is * believed to be required even though it is not documented in * the SoC BKDGs. Without this setting, there is no serial * output. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); hudson_lpc_decode(); outb(0x24, 0xCD6); outb(0x01, 0xCD7); *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ hudson_lpc_port80(); if (!cpu_init_detectedx) { post_code(0x30); f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); printk(BIOS_DEBUG, "Got past hudson_early_setup\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); post_code(0x40); AGESAWRAPPER(amdinitpost); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been * replicated in every reference design since Parmer, so it is * believed to be required even though it is not documented in * the SoC BKDGs. Without this setting, there is no serial * output. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); amd_initmmio(); hudson_lpc_decode(); outb(0x24, 0xCD6); outb(0x01, 0xCD7); *(volatile u32 *) (0xFED80000 + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ *(volatile u32 *) (0xFED80000 + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ hudson_lpc_port80(); if (!cpu_init_detectedx) { post_code(0x30); f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); printk(BIOS_DEBUG, "Got past hudson_early_setup\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); post_code(0x41); AGESAWRAPPER(amdinitenv); /* If code hangs here, please check cahaltasm.S */ disable_cache_as_ram(); } else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); AGESAWRAPPER(amdinitresume); AGESAWRAPPER(amds3laterestore); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }