/*! * Acquires 16 Bytes IV from the iv-pool * * \param drvdata Driver private context * \param iv_out_dma Array of physical IV out addresses * \param iv_out_dma_len Length of iv_out_dma array (additional elements * of iv_out_dma array are ignore) * \param iv_out_size May be 8 or 16 bytes long * \param iv_seq IN/OUT array to the descriptors sequence * \param iv_seq_len IN/OUT pointer to the sequence length * * \return int Zero for success, negative value otherwise. */ int cc_get_iv(struct cc_drvdata *drvdata, dma_addr_t iv_out_dma[], unsigned int iv_out_dma_len, unsigned int iv_out_size, struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len) { struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; unsigned int idx = *iv_seq_len; struct device *dev = drvdata_to_dev(drvdata); unsigned int t; if (iv_out_size != CC_AES_IV_SIZE && iv_out_size != CTR_RFC3686_IV_SIZE) { return -EINVAL; } if ((iv_out_dma_len + 1) > CC_IVPOOL_SEQ_LEN) { /* The sequence will be longer than allowed */ return -EINVAL; } /* check that number of generated IV is limited to max dma address * iv buffer size */ if (iv_out_dma_len > CC_MAX_IVGEN_DMA_ADDRESSES) { /* The sequence will be longer than allowed */ return -EINVAL; } for (t = 0; t < iv_out_dma_len; t++) { /* Acquire IV from pool */ hw_desc_init(&iv_seq[idx]); set_din_sram(&iv_seq[idx], (ivgen_ctx->pool + ivgen_ctx->next_iv_ofs), iv_out_size); set_dout_dlli(&iv_seq[idx], iv_out_dma[t], iv_out_size, NS_BIT, 0); set_flow_mode(&iv_seq[idx], BYPASS); idx++; } /* Bypass operation is proceeded by crypto sequence, hence must * assure bypass-write-transaction by a memory barrier */ hw_desc_init(&iv_seq[idx]); set_din_no_dma(&iv_seq[idx], 0, 0xfffff0); set_dout_no_dma(&iv_seq[idx], 0, 0, 1); idx++; *iv_seq_len = idx; /* update seq length */ /* Update iv index */ ivgen_ctx->next_iv_ofs += iv_out_size; if ((CC_IVPOOL_SIZE - ivgen_ctx->next_iv_ofs) < CC_AES_IV_SIZE) { dev_dbg(dev, "Pool exhausted, regenerating iv-pool\n"); /* pool is drained -regenerate it! */ return cc_gen_iv_pool(ivgen_ctx, iv_seq, iv_seq_len); } return 0; }
/*! * Generates CC_IVPOOL_SIZE of random bytes by * encrypting 0's using AES128-CTR. * * \param ivgen iv-pool context * \param iv_seq IN/OUT array to the descriptors sequence * \param iv_seq_len IN/OUT pointer to the sequence length */ static int cc_gen_iv_pool(struct cc_ivgen_ctx *ivgen_ctx, struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len) { unsigned int idx = *iv_seq_len; if ((*iv_seq_len + CC_IVPOOL_GEN_SEQ_LEN) > CC_IVPOOL_SEQ_LEN) { /* The sequence will be longer than allowed */ return -EINVAL; } /* Setup key */ hw_desc_init(&iv_seq[idx]); set_din_sram(&iv_seq[idx], ivgen_ctx->ctr_key, AES_KEYSIZE_128); set_setup_mode(&iv_seq[idx], SETUP_LOAD_KEY0); set_cipher_config0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); set_flow_mode(&iv_seq[idx], S_DIN_to_AES); set_key_size_aes(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE); set_cipher_mode(&iv_seq[idx], DRV_CIPHER_CTR); idx++; /* Setup cipher state */ hw_desc_init(&iv_seq[idx]); set_din_sram(&iv_seq[idx], ivgen_ctx->ctr_iv, CC_AES_IV_SIZE); set_cipher_config0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); set_flow_mode(&iv_seq[idx], S_DIN_to_AES); set_setup_mode(&iv_seq[idx], SETUP_LOAD_STATE1); set_key_size_aes(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE); set_cipher_mode(&iv_seq[idx], DRV_CIPHER_CTR); idx++; /* Perform dummy encrypt to skip first block */ hw_desc_init(&iv_seq[idx]); set_din_const(&iv_seq[idx], 0, CC_AES_IV_SIZE); set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, CC_AES_IV_SIZE); set_flow_mode(&iv_seq[idx], DIN_AES_DOUT); idx++; /* Generate IV pool */ hw_desc_init(&iv_seq[idx]); set_din_const(&iv_seq[idx], 0, CC_IVPOOL_SIZE); set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, CC_IVPOOL_SIZE); set_flow_mode(&iv_seq[idx], DIN_AES_DOUT); idx++; *iv_seq_len = idx; /* Update sequence length */ /* queue ordering assures pool readiness */ ivgen_ctx->next_iv_ofs = CC_IVPOOL_META_SIZE; return 0; }
/*! * Generates the initial pool in SRAM. * This function should be invoked when resuming driver. * * \param drvdata * * \return int Zero for success, negative value otherwise. */ int cc_init_iv_sram(struct cc_drvdata *drvdata) { struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; struct cc_hw_desc iv_seq[CC_IVPOOL_SEQ_LEN]; unsigned int iv_seq_len = 0; int rc; /* Generate initial enc. key/iv */ get_random_bytes(ivgen_ctx->pool_meta, CC_IVPOOL_META_SIZE); /* The first 32B reserved for the enc. Key/IV */ ivgen_ctx->ctr_key = ivgen_ctx->pool; ivgen_ctx->ctr_iv = ivgen_ctx->pool + AES_KEYSIZE_128; /* Copy initial enc. key and IV to SRAM at a single descriptor */ hw_desc_init(&iv_seq[iv_seq_len]); set_din_type(&iv_seq[iv_seq_len], DMA_DLLI, ivgen_ctx->pool_meta_dma, CC_IVPOOL_META_SIZE, NS_BIT); set_dout_sram(&iv_seq[iv_seq_len], ivgen_ctx->pool, CC_IVPOOL_META_SIZE); set_flow_mode(&iv_seq[iv_seq_len], BYPASS); iv_seq_len++; /* Generate initial pool */ rc = cc_gen_iv_pool(ivgen_ctx, iv_seq, &iv_seq_len); if (rc) return rc; /* Fire-and-forget */ return send_request_init(drvdata, iv_seq, iv_seq_len); }
/** * ssi_sram_mgr_const2sram_desc() - Create const descriptors sequence to * set values in given array into SRAM. * Note: each const value can't exceed word size. * * @src: A pointer to array of words to set as consts. * @dst: The target SRAM buffer to set into * @nelements: The number of words in "src" array * @seq: A pointer to the given IN/OUT descriptor sequence * @seq_len: A pointer to the given IN/OUT sequence length */ void ssi_sram_mgr_const2sram_desc( const u32 *src, ssi_sram_addr_t dst, unsigned int nelement, struct cc_hw_desc *seq, unsigned int *seq_len) { u32 i; unsigned int idx = *seq_len; for (i = 0; i < nelement; i++, idx++) { hw_desc_init(&seq[idx]); set_din_const(&seq[idx], src[i], sizeof(u32)); set_dout_sram(&seq[idx], dst + (i * sizeof(u32)), sizeof(u32)); set_flow_mode(&seq[idx], BYPASS); } *seq_len = idx; }