// The warriors there is no i2c master reset function
static void i2c0_master_reset(u8 i2c_id, u16 i2c_clock)
{
u32 mask = 0;
u32 ctrl = 0;
u32 bit = 0;
u32 rtmp = 0;
switch(i2c_id)
{
case 0:
mask = R_RST_GLOBAL0_MASK;
ctrl = R_RST_GLOBAL0_CTRL;
bit = 9;
break;
case 1:
mask = R_RST_GLOBAL0_MASK;
ctrl = R_RST_GLOBAL0_CTRL;
bit = 10;
break;
case 2:
mask = R_RST_GLOBAL1_MASK;
ctrl = R_RST_GLOBAL1_CTRL;
bit = 4;
break;
}
rtmp = hal_get_u32((volatile unsigned long *) mask);
rtmp &= ~(1 << bit);
hal_put_u32((volatile unsigned long *) mask, rtmp);
rtmp = hal_get_u32((volatile unsigned long *) ctrl);
rtmp &= ~(1 << bit);
hal_put_u32((volatile unsigned long *) ctrl, rtmp);
I2C_DELAY_US(1000);
rtmp = hal_get_u32((volatile unsigned long *) mask);
rtmp |= (1 << bit);
hal_put_u32((volatile unsigned long *) mask, rtmp);
rtmp = hal_get_u32((volatile unsigned long *) ctrl);
rtmp |= (1 << bit);
hal_put_u32((volatile unsigned long *) ctrl, rtmp);
if(i2c_clock != 0)
{
i2c0_init(i2c_id,i2c_clock);
}
else
{
i2c0_init(i2c_id, I2C_DEF_CLK_KHZ);
}
I2C_DELAY_US(1000);
}
static RET_CODE i2c_jazz_open(lld_i2c_t *p_lld, i2c_cfg_t *p_cfg)
{
i2c_ctrller_jazz_priv_t *p_priv = NULL;
drv_dev_t *p_dev = NULL;
device_base_t *p_base = NULL;
////OS_PRINTF("In i2c_wactrller_open\n");
p_dev = DEV_FIND_BY_LLD(drv_dev_t, p_lld);
p_base = p_dev->p_base;
if(p_lld->p_priv != NULL)
{
mtos_free(p_lld->p_priv);
p_lld->p_priv = NULL;
}
p_priv = p_lld->p_priv = mtos_malloc(sizeof(i2c_ctrller_jazz_priv_t));
if(NULL == p_cfg)
{
p_priv->i2c_clk = I2C_DEF_CLK_KHZ;
p_priv->i2c_id = 0;
p_base->lock_mode = OS_MUTEX_LOCK;
}
else
{
p_priv->i2c_clk = p_cfg->bus_clk_khz;
p_priv->i2c_id = p_cfg->i2c_id;
p_base->lock_mode = p_cfg->lock_mode;
}
i2c0_init(p_priv->i2c_id, p_priv->i2c_clk);
return SUCCESS;
}
void ADCHS_stop(airspy_samplerate_t conf_num)
{
start_stop_adchs_m4(conf_num, STOP_ADCHS_CMD);
/* Re-Init I2C0 & I2C1 after PLL1 frequency is modified */
i2c0_init(AIRSPY_I2C0_PLL1_LS_HS_CONF_VAL); /* Si5351C I2C peripheral */
i2c1_init(AIRSPY_I2C1_PLL1_LS_CONF_VAL); /* R820T I2C peripheral */
disable_r820t_power();
}
void ADCHS_start(airspy_samplerate_t conf_num)
{
start_stop_adchs_m4(conf_num, START_ADCHS_CMD);
enable_r820t_power();
/* Re-Init I2C0 & I2C1 after PLL1 frequency is modified (for I2C1 also because PowerOn on R820T) */
i2c0_init(AIRSPY_I2C0_PLL1_LS_HS_CONF_VAL); /* Si5351C I2C peripheral */
i2c1_init(AIRSPY_I2C1_PLL1_HS_CONF_VAL); /* R820T I2C peripheral */
r820t_init(&r820t_conf_rw, airspy_m0_conf[conf_num].r820t_if_freq);
r820t_set_if_bandwidth(&r820t_conf_rw, airspy_m0_conf[conf_num].r820t_if_bw);
phase = 1;
}
static RET_CODE i2c_jazz_ioctrl(lld_i2c_t *p_lld, u32 cmd, u32 param)
{
i2c_ctrller_jazz_priv_t *p_priv = (i2c_ctrller_jazz_priv_t *)p_lld->p_priv;
switch(cmd)
{
case I2C_IOCTRL_SET_CLOCK:
i2c0_init(p_priv->i2c_id, param);
break;
case I2C_IOCTRL_STOP:
i2c0_stop(p_priv->i2c_id);
break;
default:
break;
}
return SUCCESS;
}
static inline void main_init( void ) {
mcu_init();
sys_time_register_timer((1./PERIODIC_FREQUENCY), NULL);
mb_tacho_init();
#if defined USE_TWI_CONTROLLER
i2c0_init();
mb_twi_controller_init();
#endif
mb_servo_init();
mb_servo_set_range( 1090000, 1910000 );
mb_current_init();
mb_scale_init();
uart0_init();
mb_mode_init();
mcu_int_enable();
}
extern "C" int main() {
turn_on_crystal_oscillator();
start_system_pll();
start_usb_pll();
set_main_clock_to_system_pll();
enable_peripheral_clocks();
serial_init();
configure_pins();
delay(1000000);
//enable_clock_output();
NVIC.enable_interrupts();
//serial_write_string("main():loop");
//serial_write_line();
// Power for FPGA
v1p2_enable(); // FPGA VCCINT
v2p5_enable(); // FPGA PLLs?
v1p8_enable(); // FPGA VCCIOs, DDR2.
v1p1_enable(); // USB internal voltage
delay(1000000);
// Power for the clock generator.
// V3P3A must be turned on *after* V1P8 to satisfy
// Si5351C requirement.
v3p3a_enable();
delay(1000000);
// I2C configuration
i2c0_init(500);
// Give Si5351C time to power up?
delay(100000);
si5351c_disable_all_outputs();
//si5351c_disable_oeb_pin_control();
si5351c_power_down_all_clocks();
si5351c_set_crystal_configuration();
si5351c_enable_xo_and_ms_fanout();
si5351c_configure_pll_sources_for_xtal();
si5351c_configure_pll1_multisynth();
si5351c_configure_multisynth(4, 1536, 0, 1, 0); // 50MHz
si5351c_configure_multisynth(5, 1536, 0, 1, 0); // 50MHz
si5351c_configure_multisynths_6_and_7();
si5351c_configure_clock_control();
si5351c_enable_clock_outputs();
clockgen_output_enable();
fe_enable();
while(true) {
//write_led_status(read_fpga_conf_done());
write_led_status(1);
delay(1000000);
write_led_status(0);
delay(1000000);
}
return 0;
}
void mcu_init(void)
{
mcu_arch_init();
#ifdef PERIPHERALS_AUTO_INIT
sys_time_init();
#ifdef USE_LED
led_init();
#endif
/* for now this means using spektrum */
#if defined RADIO_CONTROL & defined RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT & defined RADIO_CONTROL_BIND_IMPL_FUNC
RADIO_CONTROL_BIND_IMPL_FUNC();
#endif
#ifdef USE_UART0
uart0_init();
#endif
#ifdef USE_UART1
uart1_init();
#endif
#ifdef USE_UART2
uart2_init();
#endif
#ifdef USE_UART3
uart3_init();
#endif
#ifdef USE_UART4
uart4_init();
#endif
#ifdef USE_UART5
uart5_init();
#endif
#ifdef USE_I2C0
i2c0_init();
#endif
#ifdef USE_I2C1
i2c1_init();
#endif
#ifdef USE_I2C2
i2c2_init();
#endif
#ifdef USE_ADC
adc_init();
#endif
#ifdef USE_USB_SERIAL
VCOM_init();
#endif
#if USE_SPI
#if SPI_MASTER
#if USE_SPI0
spi0_init();
#endif
#if USE_SPI1
spi1_init();
#endif
#if USE_SPI2
spi2_init();
#endif
#if USE_SPI3
spi3_init();
#endif
spi_init_slaves();
#endif // SPI_MASTER
#if SPI_SLAVE
#if USE_SPI0_SLAVE
spi0_slave_init();
#endif
#if USE_SPI1_SLAVE
spi1_slave_init();
#endif
#if USE_SPI2_SLAVE
spi2_slave_init();
#endif
#if USE_SPI3_SLAVE
spi3_slave_init();
#endif
#endif // SPI_SLAVE
#endif // USE_SPI
#ifdef USE_DAC
dac_init();
#endif
#else
INFO("PERIPHERALS_AUTO_INIT not enabled! Peripherals (including sys_time) need explicit initialization.")
#endif /* PERIPHERALS_AUTO_INIT */
}
void init_ap( void ) {
#ifndef SINGLE_MCU /** init done in main_fbw in single MCU */
hw_init();
sys_time_init();
#ifdef LED
led_init();
#endif
#ifdef ADC
adc_init();
#endif
#endif /* SINGLE_MCU */
/************* Sensors initialization ***************/
#ifdef USE_INFRARED
ir_init();
#endif
#ifdef USE_GYRO
gyro_init();
#endif
#ifdef USE_GPS
gps_init();
#endif
#ifdef USE_UART0
Uart0Init();
#endif
#ifdef USE_UART1
Uart1Init();
#endif
#ifdef USE_UART2
Uart2Init();
#endif
#ifdef USE_UART3
Uart3Init();
#endif
#ifdef USE_USB_SERIAL
VCOM_init();
#endif
#ifdef USE_GPIO
GpioInit();
#endif
#ifdef USE_I2C0
i2c0_init();
#endif
#ifdef USE_I2C1
i2c1_init();
#endif
#ifdef USE_I2C2
i2c2_init();
#endif
/************* Links initialization ***************/
#if defined USE_SPI
spi_init();
#endif
#if defined MCU_SPI_LINK
link_mcu_init();
#endif
#ifdef MODEM
modem_init();
#endif
/************ Internal status ***************/
h_ctl_init();
v_ctl_init();
estimator_init();
#ifdef ALT_KALMAN
alt_kalman_init();
#endif
nav_init();
modules_init();
/** - start interrupt task */
int_enable();
/** wait 0.5s (historical :-) */
sys_time_usleep(500000);
#if defined GPS_CONFIGURE
gps_configure_uart();
#endif
#if defined DATALINK
#if DATALINK == XBEE
xbee_init();
#endif
#endif /* DATALINK */
#if defined AEROCOMM_DATA_PIN
IO0DIR |= _BV(AEROCOMM_DATA_PIN);
IO0SET = _BV(AEROCOMM_DATA_PIN);
#endif
power_switch = FALSE;
/************ Multi-uavs status ***************/
#ifdef TRAFFIC_INFO
traffic_info_init();
#endif
}
/*
Configure PLL1 to min speed (48MHz) => see cpu_clock_pll1_low_speed() .
Configure PLL0USB @480MHz for USB0.
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1, APB3.
*/
void sys_clock_init(const airspy_sys_clock_t* const pt_airspy_sys_conf)
{
/* After boot the CPU runs at 96 MHz */
/* cpu runs from: IRC (12MHz) >> PLL M = 24, FCCO @ 288 MHz direct mode >> IDIVC = 4 >> 96 MHz */
/*
* 12MHz clock is entering LPC XTAL1/OSC input now.
*/
/* set xtal oscillator to low frequency mode */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF;
/* power on the oscillator and wait until stable */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE;
/* Wait at least 250us after Crystal Power ON (Wait for crystal to stabilize)
defined in User Manual 10503.pdf Rev1.8 See Fig 30. BASE_M4_CLK ramp-up procedure
*/
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* Use CGU_SRC_XTAL as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK);
/* Use CGU_SRC_XTAL as clock source for Peripheral */
CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_XTAL);
/* Use CGU_SRC_XTAL as clock source for APB1 */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
/* Use CGU_SRC_XTAL as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
/* ********************** */
/* SI5351c configuration */
/* ********************** */
/*
* xxMHz clock is entering LPC GP_CLKIN (from SI5351C) input now.
* AirSpy clocks:
* CLK0 -> R820T xxMHz (XTAL_I)
* CLK1 -> LPC4370 RTC 32KHz
* CLK2 -> SGPIO Clock (not used for future)
* CLK3 -> NC
* CLK4 -> NC
* CLK5 -> NC
* CLK6 -> NC
* CLK7 -> LPC4370 Main Clock xxMHz.
*/
/* Configure I2C0 (for SI5351C) to about 375kHz (12MHz/(2*16)=0.375MHz) when we switch over to APB1 clock = 12MHz */
i2c0_init(16);
si5351c_disable_oeb_pin_control();
/* Programming the Si5351 via I2C http://community.silabs.com/t5/Silicon-Labs-Knowledge-Base/Programming-the-Si5351-via-I2C/ta-p/112251
*/
si5351c_disable_all_outputs();
si5351c_init_fanout();
si5351c_power_down_all_clocks();
si5351c_init_xtal();
si5351c_read[0] = si5351c_read_single(0);
/* Configure and enable SI5351C clocks */
si5351c_read[1] = (si5351c_read_single(0) & SI5351C_REG0_CLKIN_LOS);
/* CLKIN Loss Of Signal (LOS) ? */
if(si5351c_read[1] == SI5351C_REG0_CLKIN_LOS)
si5351c_airspy_config(AIRSPY_SI5351C_CONFIG_XTAL);
else
si5351c_airspy_config(AIRSPY_SI5351C_CONFIG_CLKIN);
si5351c_read[2] = si5351c_read_single(0);
si5351c_init_pll_soft_reset();
si5351c_enable_clock_outputs();
/* Wait at least 300us after SI5351C Clock Enable */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
si5351c_read[3] = si5351c_read_single(0);
/* ********************************************************************* */
/* M4/M0 core, Peripheral, APB1, APB3 Configuration (PLL1 clock source) */
/* ********************************************************************* */
/* Configure PLL1 with CGU_SRC_GP_CLKIN as source clock */
cpu_clock_pll1_low_speed(&pt_airspy_sys_conf->pll1_ls);
/* Configure I2C0 (for SI5351C) to 400kHz when we switch over to APB1 clock = PLL1 */
i2c0_init(AIRSPY_I2C0_PLL1_LS_HS_CONF_VAL);
/* Configure I2C1 (for R820T) to 400kHz when we switch over to APB3 clock = PLL1 */
i2c1_init(AIRSPY_I2C1_PLL1_LS_CONF_VAL);
/* ************************************************** */
/* Connect PLL1 to M4/M0 core, Peripheral, APB1, APB3 */
/* ************************************************** */
/* Use PLL1 as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK);
/* Switch peripheral clock over to use PLL1 */
CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB1 clock over to use PLL1 */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB3 clock over to use PLL1 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
/* **************************************************** */
/* PLL0USB & USB0 Configuration (GP_CLKIN clock source) */
/* **************************************************** */
/* Use CGU_SRC_GP_CLKIN as clock source for PLL0USB */
CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD
| CGU_PLL0USB_CTRL_AUTOBLOCK
| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_GP_CLKIN);
while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK);
/* configure PLL0USB to produce 480 MHz clock from CGU_SRC_GP_CLKIN */
CGU_PLL0USB_MDIV = pt_airspy_sys_conf->pll0_usb_mdiv;
CGU_PLL0USB_NP_DIV = pt_airspy_sys_conf->pll0_usb_npdiv;
CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD
| pt_airspy_sys_conf->pll0usb_ctrl_flags
| CGU_PLL0USB_CTRL_CLKEN);
/* Power on PLL0USB and wait until stable */
CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD;
while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK));
/* Use PLL0USB as clock source for USB0 */
CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK
| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
/* ****************************************** */
/* Disable/PowerDown unused clock/peripherals */
/* ****************************************** */
CREG_CREG6 |= (1<<17); // PowerDown RNG
/* Disable XTAL because GP_CLKIN is used from SI5351C instead */
/* Switch off the oscillator */
CGU_XTAL_OSC_CTRL = CGU_XTAL_OSC_CTRL_ENABLE;
CGU_BASE_SAFE_CLK = CGU_BASE_USB1_CLK_PD;
// CGU_BASE_USB0_CLK is used for USB0 HS
// CGU_BASE_M0_CLK is used
/* Switch off USB1 clock */
CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_PD;
// CGU_BASE_M4_CLK is used
CGU_BASE_SPIFI_CLK = CGU_BASE_SPIFI_CLK_PD;
/* Switch off SPI clock */
CGU_BASE_SPI_CLK = CGU_BASE_SPI_CLK_PD;
/* Switch off PHY RX & TX clock */
CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD;
CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD;
// CGU_BASE_APB1_CLK is used for I2C0
// CGU_BASE_APB3_CLK is used for I2C1
/* Switch off LCD clock */
CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD;
// CGU_BASE_ADCHS_CLK is used
/* Switch off SDIO clock */
CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD;
CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_PD;
#ifdef AIRSPY_NOS
/* Switch off SSP1 clock */
CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_PD;
#else /* AIRSPY One/Demo */
//CGU_BASE_SSP1_CLK is used for LED
#endif
/* Switch off UART0 to 3 clock */
CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD;
CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD;
CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD;
CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD;
/* Switch off OUT clocks */
CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD;
/* Reserved/Undocumented clocks power down */
CGU_OUTCLK_21_CTRL = 1;
CGU_OUTCLK_22_CTRL = 1;
CGU_OUTCLK_23_CTRL = 1;
CGU_OUTCLK_24_CTRL = 1;
/* Switch off AUDIO clock */
CGU_BASE_APLL_CLK = CGU_BASE_APLL_CLK_PD;
CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD;
CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD;
/* Switch off IDIV C,D,E disabled */
CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD;
CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD;
CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD;
/*
// Power down M4 branches, but not BUS, GPIO, CREG and M0 & M4 CORE clock
*/
//CCU1_CLK_M4_BUS_CFG &= ~(1);
CCU1_CLK_M4_SPIFI_CFG &= ~(1);
//CCU1_CLK_M4_GPIO_CFG &= ~(1);
CCU1_CLK_M4_LCD_CFG &= ~(1);
CCU1_CLK_M4_ETHERNET_CFG &= ~(1);
//CCU1_CLK_M4_USB0_CFG &= ~(1);
CCU1_CLK_M4_EMC_CFG &= ~(1);
CCU1_CLK_M4_SDIO_CFG &= ~(1);
//CCU1_CLK_M4_DMA_CFG &= ~(1);
//CCU1_CLK_M4_M4CORE_CFG &= ~(1);
CCU1_CLK_M4_SCT_CFG &= ~(1);
CCU1_CLK_M4_USB1_CFG &= ~(1);
CCU1_CLK_M4_EMCDIV_CFG &= ~(1);
//CCU1_CLK_M4_M0APP_CFG &= ~(1);
//CCU1_CLK_M4_VADC_CFG &= ~(1);
CCU1_CLK_M4_WWDT_CFG &= ~(1);
CCU1_CLK_M4_USART0_CFG &= ~(1);
CCU1_CLK_M4_UART1_CFG &= ~(1);
CCU1_CLK_M4_SSP0_CFG &= ~(1);
#ifdef AIRSPY_NOS
CCU1_CLK_M4_SSP1_CFG &= ~(1);
#else /* AIRSPY One/Demo */
//CCU1_CLK_M4_SSP1_CFG is used for LED
#endif
CCU1_CLK_M4_TIMER0_CFG &= ~(1);
CCU1_CLK_M4_TIMER1_CFG &= ~(1);
//CCU1_CLK_M4_SCU_CFG &= ~(1);
//CCU1_CLK_M4_CREG_CFG &= ~(1);
CCU1_CLK_M4_RITIMER_CFG &= ~(1);
CCU1_CLK_M4_USART2_CFG &= ~(1);
CCU1_CLK_M4_USART3_CFG &= ~(1);
CCU1_CLK_M4_TIMER2_CFG &= ~(1);
CCU1_CLK_M4_TIMER3_CFG &= ~(1);
CCU1_CLK_M4_QEI_CFG &= ~(1);
CCU1_CLK_PERIPH_SGPIO_CFG &= ~(1);
/* ******************************************** */
/* ADCHS Configuration (GP_CLKIN clock source) */
/* ******************************************** */
sys_clock_samplerate(&airspy_m4_conf[0]);
}
/**
* Configures i2c0 to work with LM75 sensor
*
* @param clk Desired i2c0 clock frequency in hertz
*/
void lm75_init(unsigned int clk)
{
i2c0_init(clk);
}
int main()
{
unsigned int num;
unsigned char ret = 0;
#ifdef MMU_ON
mmu_init();
#endif
led_init();
key_init();
irq_init();
uart0_init();
lcd_init();
i2c0_init();
lcd_clear_screen(0x000000);
dm9000_init();
printf("First write address of 0x0,");
at24cxx_write(0x0, 0xAA); //往设备内存0地址写入0xAA
ret = at24cxx_read(0x0); //读设备内存0地址里面的数据
printf("the value in address 0x0 = %x\r\n",ret);
printf("Second write address of 0x1,");
at24cxx_write(0x1,0x33);
ret = at24cxx_read(0x1);
printf("the value in address 0x1 = %x\r\n",ret);
// dm9000_arp();
while(1)
{
printf("\r\n");
printf("========= Boot for S5pv210 Main Menu =========\r\n");
printf("========= designed by KungfuMonkey =========\r\n");
printf("\r\n");
printf("1.ARP Request for PC MAC\r\n");
printf("2.Download Linux Kernel to SDRAM\r\n");
printf("3.Run the linux\r\n");
scanf("%d\r\n",&num);
printf("%d\r\n",num);
switch(num)
{
case 1:
arp_request();
break;
case 2:
tftp_send_request("zImage");
break;
case 3:
boot_linux();
break;
default:
printf("Error: wrong selection!\r\n");
break;
}
}
return 0;
}
