static void i2c_init(void) { int i, p, p_ch; /* Configure GPIOs */ gpio_config_module(MODULE_I2C, 1); #ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7 /* bit7, 0: SMCLK2 is located on GPF6, 1: SMCLK2 is located on GPC7 */ IT83XX_GPIO_GRC7 |= 0x80; #endif /* Enable I2C function. */ for (i = 0; i < i2c_ports_used; i++) { /* I2c port mapping. */ p = i2c_ports[i].port; clock_enable_peripheral(i2c_ctrl_regs[p].clock_gate, 0, 0); if (p < I2C_STANDARD_PORT_COUNT) { /* * bit0, The SMBus host interface is enabled. * bit1, Enable to communicate with I2C device * and support I2C-compatible cycles. * bit4, This bit controls the reset mechanism * of SMBus master to handle the SMDAT * line low if 25ms reg timeout. */ IT83XX_SMB_HOCTL2(p) = 0x11; /* * bit1, Kill SMBus host transaction. * bit0, Enable the interrupt for the master interface. */ IT83XX_SMB_HOCTL(p) = 0x03; IT83XX_SMB_HOCTL(p) = 0x01; /* W/C host status register */ IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT; IT83XX_SMB_HOCTL2(p) = 0x00; } else { /* Shift register */ p_ch = i2c_ch_reg_shift(p); switch (p) { case IT83XX_I2C_CH_D: #ifndef CONFIG_UART_HOST /* Enable SMBus D channel */ IT83XX_GPIO_GRC2 |= 0x20; #endif break; case IT83XX_I2C_CH_E: /* Enable SMBus E channel */ IT83XX_GCTRL_PMER1 |= 0x01; break; case IT83XX_I2C_CH_F: /* Enable SMBus F channel */ IT83XX_GCTRL_PMER1 |= 0x02; break; } /* Software reset */ IT83XX_I2C_DHTR(p_ch) |= 0x80; IT83XX_I2C_DHTR(p_ch) &= 0x7F; /* State reset and hardware reset */ IT83XX_I2C_CTR(p_ch) = 0x11; IT83XX_I2C_CTR(p_ch) = 0x00; /* Set time out condition */ IT83XX_I2C_TOR(p_ch) = 0xFF; IT83XX_I2C_T_BUF(p_ch) = 0x3F; /* * bit3, Acknowledge * bit5, Master mode * bit6, Interrupt enable */ IT83XX_I2C_CTR(p_ch) = 0x68; /* * bit1, Module enable * bit4-6 Support number of devices */ IT83XX_I2C_CTR1(p_ch) = 0x00; } pdata[i].task_waiting = TASK_ID_INVALID; } i2c_freq_changed(); for (i = 0; i < I2C_PORT_COUNT; i++) { /* Use default timeout */ i2c_set_timeout(i, 0); } }
static void i2c_init(void) { int i; /* Configure pins from GPIOs to I2Cs */ gpio_config_module(MODULE_I2C, 1); /* Enable clock for I2C peripheral */ clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK, CGC_MODE_RUN | CGC_MODE_SLEEP); /* Set I2C freq */ i2c_freq_changed(); /* * initialize smb status and register */ for (i = 0; i < i2c_ports_used; i++) { int port = i2c_ports[i].port; int ctrl = i2c_port_to_controller(port); volatile struct i2c_status *p_status = i2c_stsobjs + ctrl; /* Configure pull-up for SMB interface pins */ /* Enable 3.3V pull-up or turn to 1.8V support */ if (port == NPCX_I2C_PORT0_0) { #ifdef NPCX_I2C0_0_1P8V SET_BIT(NPCX_LV_GPIO_CTL0, NPCX_LV_GPIO_CTL0_SC0_0_LV); SET_BIT(NPCX_LV_GPIO_CTL0, NPCX_LV_GPIO_CTL0_SD0_0_LV); #else SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 0)); #endif } else if (port == NPCX_I2C_PORT0_1) { #ifdef NPCX_I2C0_1_1P8V SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL0_SC0_1_LV); SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL0_SD0_1_LV); #else SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 1)); #endif } else if (port == NPCX_I2C_PORT1) { #ifdef NPCX_I2C1_1P8V SET_BIT(NPCX_LV_GPIO_CTL0, NPCX_LV_GPIO_CTL0_SC1_0_LV); SET_BIT(NPCX_LV_GPIO_CTL0, NPCX_LV_GPIO_CTL0_SD1_0_LV); #else SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 0)); #endif } else if (port == NPCX_I2C_PORT2) { #ifdef NPCX_I2C2_1P8V SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL1_SC2_0_LV); SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL1_SD2_0_LV); #else SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 0)); #endif } else if (port == NPCX_I2C_PORT3) { #ifdef NPCX_I2C3_1P8V SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL1_SC3_0_LV); SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL1_SD3_0_LV); #else SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 0)); #endif } /* Enable module - before configuring CTL1 */ SET_BIT(NPCX_SMBCTL2(ctrl), NPCX_SMBCTL2_ENABLE); /* status init */ p_status->oper_state = SMB_IDLE; /* Reset task ID */ p_status->task_waiting = TASK_ID_INVALID; /* Enable event and error interrupts */ task_enable_irq(i2c_irqs[ctrl]); /* Use default timeout. */ i2c_set_timeout(port, 0); } }