void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc)
{
unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
desc->chip->eoi(irq);
}
static int pSeries_irq_cascade(struct pt_regs *regs, void *data)
{
if (chrp_int_ack_special)
return readb(chrp_int_ack_special);
else
return i8259_irq(smp_processor_id());
}
int
xics_get_irq(struct pt_regs *regs)
{
u_int cpu = smp_processor_id();
u_int vec;
int irq;
vec = ops->xirr_info_get(cpu);
/* (vec >> 24) == old priority */
vec &= 0x00ffffff;
/* for sanity, this had better be < NR_IRQS - 16 */
if( vec == xics_irq_8259_cascade_real ) {
irq = i8259_irq(cpu);
if(irq == -1) {
/* Spurious cascaded interrupt. Still must ack xics */
xics_end_irq(XICS_IRQ_OFFSET + xics_irq_8259_cascade);
irq = -1;
}
} else if( vec == XICS_IRQ_SPURIOUS ) {
irq = -1;
printk("spurious PPC interrupt!\n");
} else
irq = real_irq_to_virt(vec) + XICS_IRQ_OFFSET;
return irq;
}
/*
* hwint 1 deals with EISA and SCSI interrupts,
*
* The EISA_INT bit in CSITPEND is high active, all others are low active.
*/
static void pcimt_hwint1(void)
{
u8 pend = *(volatile char *)PCIMT_CSITPEND;
unsigned long flags;
if (pend & IT_EISA) {
int irq;
/*
* Note: ASIC PCI's builtin interrupt acknowledge feature is
* broken. Using it may result in loss of some or all i8259
* interrupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
*/
irq = i8259_irq();
if (unlikely(irq < 0))
return;
do_IRQ(irq);
}
if (!(pend & IT_SCSI)) {
flags = read_c0_status();
clear_c0_status(ST0_IM);
do_IRQ(PCIMT_IRQ_SCSI);
write_c0_status(flags);
}
}
static int ppc7d_get_irq(void)
{
int irq;
irq = mv64360_get_irq();
if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
irq = i8259_irq();
return irq;
}
static void mpc8544_8259_cascade(unsigned int irq, struct irq_desc *desc)
{
unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ) {
generic_handle_irq(cascade_irq);
}
desc->chip->eoi(irq);
}
/*
* Support code for cascading to 8259 interrupt controllers
*/
static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
{
unsigned int cascade_irq = i8259_irq();
if (cascade_irq)
generic_handle_irq(cascade_irq);
/* Let xilinx_intc end the interrupt */
desc->chip->unmask(irq);
}
static int ppc7d_get_irq(struct pt_regs *regs)
{
int irq;
irq = mv64360_get_irq(regs);
if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
irq = i8259_irq(regs);
return irq;
}
static void mvme5100_8259_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
chip->irq_eoi(&desc->irq_data);
}
static void i8259_irqdispatch(void)
{
int irq;
irq = i8259_irq();
if (irq >= 0)
do_IRQ(irq);
else
spurious_interrupt();
}
static void mpc86xx_8259_cascade(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();
if (cascade_irq)
generic_handle_irq(cascade_irq);
chip->irq_eoi(&desc->irq_data);
}
static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id, struct pt_regs *regs)
{
u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
if (temp & (1 << 28)) {
i8259_irq(regs);
mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28)));
return IRQ_HANDLED;
}
return IRQ_NONE;
}
/* ISA irq handler */
static irqreturn_t sni_isa_irq_handler(int dummy, void *p)
{
int irq;
irq = i8259_irq();
if (unlikely(irq < 0))
return IRQ_NONE;
generic_handle_irq(irq);
return IRQ_HANDLED;
}
static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned int cascade_irq = i8259_irq();
if (cascade_irq)
generic_handle_irq(cascade_irq);
/* */
chip->irq_unmask(&desc->irq_data);
}
int
adir_get_irq(struct pt_regs *regs)
{
int irq;
if ((irq = adir_onboard_pic_get_irq()) < 0)
return irq;
if (irq == ADIR_IRQ_VT82C686_INTR)
irq = i8259_irq(regs);
return irq;
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause();
if (pending & 0x8000) {
do_IRQ(Q_COUNT_COMPARE_IRQ);
return;
}
if (pending & 0x0400) {
int irq = i8259_irq();
if (likely(irq >= 0))
do_IRQ(irq);
return;
}
}
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
unsigned int pending = read_c0_status() & read_c0_cause();
if (pending & 0x8000) {
ll_timer_interrupt(Q_COUNT_COMPARE_IRQ, regs);
return;
}
if (pending & 0x0400) {
int irq = i8259_irq();
if (likely(irq >= 0))
do_IRQ(irq, regs);
return;
}
}
asmlinkage void cobalt_irq(struct pt_regs *regs)
{
unsigned int pending = read_c0_status() & read_c0_cause();
if (pending & CAUSEF_IP2) { /* int 18 */
unsigned long irq_src = GALILEO_INL(GT_INTRCAUSE_OFS);
/* Check for timer irq ... */
if (irq_src & GALILEO_T0EXP) {
/* Clear the int line */
GALILEO_OUTL(0, GT_INTRCAUSE_OFS);
do_IRQ(COBALT_TIMER_IRQ, regs);
}
return;
}
if (pending & CAUSEF_IP6) { /* int 22 */
int irq = i8259_irq();
if (irq >= 0)
do_IRQ(irq, regs);
return;
}
if (pending & CAUSEF_IP3) { /* int 19 */
do_IRQ(COBALT_ETH0_IRQ, regs);
return;
}
if (pending & CAUSEF_IP4) { /* int 20 */
do_IRQ(COBALT_ETH1_IRQ, regs);
return;
}
if (pending & CAUSEF_IP5) { /* int 21 */
do_IRQ(COBALT_SERIAL_IRQ, regs);
return;
}
if (pending & CAUSEF_IP7) { /* int 23 */
do_IRQ(COBALT_QUBE_SLOT_IRQ, regs);
return;
}
}
int toshiba_rbtx4927_irq_nested(int sw_irq)
{
u32 level3;
level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
if (level3) {
sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
goto RETURN;
}
}
#ifdef CONFIG_TOSHIBA_FPCIB0
if (tx4927_using_backplane) {
int irq = i8259_irq();
if (irq >= 0)
sw_irq = irq;
}
#endif
RETURN:
return (sw_irq);
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
int irq;
if (pending & CAUSEF_IP2)
gt641xx_irq_dispatch();
else if (pending & CAUSEF_IP6) {
irq = i8259_irq();
if (irq < 0)
spurious_interrupt();
else
do_IRQ(irq);
} else if (pending & CAUSEF_IP3)
do_IRQ(MIPS_CPU_IRQ_BASE + 3);
else if (pending & CAUSEF_IP4)
do_IRQ(MIPS_CPU_IRQ_BASE + 4);
else if (pending & CAUSEF_IP5)
do_IRQ(MIPS_CPU_IRQ_BASE + 5);
else if (pending & CAUSEF_IP7)
do_IRQ(MIPS_CPU_IRQ_BASE + 7);
else
spurious_interrupt();
}
int i8259_irq_cascade(struct pt_regs *regs, void *unused)
{
return i8259_irq(regs);
}