static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, size_t start, size_t length, enum dma_data_direction direction) { struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); struct drm_device *dev = obj->base.dev; int ret; bool write = (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE); ret = i915_mutex_lock_interruptible(dev); if (ret) return ret; ret = i915_gem_object_set_to_cpu_domain(obj, write); mutex_unlock(&dev->struct_mutex); return ret; }
static int render_state_setup(const int gen, const struct intel_renderstate_rodata *rodata, struct i915_render_state *so) { const u64 goffset = i915_gem_obj_ggtt_offset(so->obj); u32 reloc_index = 0; u32 * const d = so->batch; unsigned int i = 0; int ret; if (!rodata || rodata->batch_items * 4 > so->size) return -EINVAL; ret = i915_gem_object_set_to_cpu_domain(so->obj, true); if (ret) return ret; while (i < rodata->batch_items) { u32 s = rodata->batch[i]; if (reloc_index < rodata->reloc_items && i * 4 == rodata->reloc[reloc_index]) { s += goffset & 0xffffffff; /* We keep batch offsets max 32bit */ if (gen >= 8) { if (i + 1 >= rodata->batch_items || rodata->batch[i + 1] != 0) return -EINVAL; d[i] = s; i++; s = (goffset & 0xffffffff00000000ull) >> 32; } reloc_index++; } d[i] = s; i++; }
static int render_state_setup(struct render_state *so) { const struct intel_renderstate_rodata *rodata = so->rodata; unsigned int i = 0, reloc_index = 0; struct page *page; u32 *d; int ret; ret = i915_gem_object_set_to_cpu_domain(so->obj, true); if (ret) return ret; page = i915_gem_object_get_dirty_page(so->obj, 0); d = kmap(page); while (i < rodata->batch_items) { u32 s = rodata->batch[i]; if (i * 4 == rodata->reloc[reloc_index]) { u64 r = s + so->ggtt_offset; s = lower_32_bits(r); if (so->gen >= 8) { if (i + 1 >= rodata->batch_items || rodata->batch[i + 1] != 0) { ret = -EINVAL; goto err_out; } d[i++] = s; s = upper_32_bits(r); } reloc_index++; } d[i++] = s; } while (i % CACHELINE_DWORDS) OUT_BATCH(d, i, MI_NOOP); so->aux_batch_offset = i * sizeof(u32); OUT_BATCH(d, i, MI_BATCH_BUFFER_END); so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset; /* * Since we are sending length, we need to strictly conform to * all requirements. For Gen2 this must be a multiple of 8. */ so->aux_batch_size = ALIGN(so->aux_batch_size, 8); kunmap(page); ret = i915_gem_object_set_to_gtt_domain(so->obj, false); if (ret) return ret; if (rodata->reloc[reloc_index] != -1) { DRM_ERROR("only %d relocs resolved\n", reloc_index); return -EINVAL; } return 0; err_out: kunmap(page); return ret; }
static int render_state_setup(struct render_state *so) { struct drm_device *dev = so->vma->vm->dev; const struct intel_renderstate_rodata *rodata = so->rodata; const bool has_64bit_reloc = INTEL_GEN(dev) >= 8; unsigned int i = 0, reloc_index = 0; struct page *page; u32 *d; int ret; ret = i915_gem_object_set_to_cpu_domain(so->vma->obj, true); if (ret) return ret; page = i915_gem_object_get_dirty_page(so->vma->obj, 0); d = kmap(page); while (i < rodata->batch_items) { u32 s = rodata->batch[i]; if (i * 4 == rodata->reloc[reloc_index]) { u64 r = s + so->vma->node.start; s = lower_32_bits(r); if (has_64bit_reloc) { if (i + 1 >= rodata->batch_items || rodata->batch[i + 1] != 0) { ret = -EINVAL; goto err_out; } d[i++] = s; s = upper_32_bits(r); } reloc_index++; } d[i++] = s; } while (i % CACHELINE_DWORDS) OUT_BATCH(d, i, MI_NOOP); so->aux_batch_offset = i * sizeof(u32); if (HAS_POOLED_EU(dev)) { /* * We always program 3x6 pool config but depending upon which * subslice is disabled HW drops down to appropriate config * shown below. * * In the below table 2x6 config always refers to * fused-down version, native 2x6 is not available and can * be ignored * * SNo subslices config eu pool configuration * ----------------------------------------------------------- * 1 3 subslices enabled (3x6) - 0x00777000 (9+9) * 2 ss0 disabled (2x6) - 0x00777000 (3+9) * 3 ss1 disabled (2x6) - 0x00770000 (6+6) * 4 ss2 disabled (2x6) - 0x00007000 (9+3) */ u32 eu_pool_config = 0x00777000; OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); OUT_BATCH(d, i, eu_pool_config); OUT_BATCH(d, i, 0); OUT_BATCH(d, i, 0); OUT_BATCH(d, i, 0); } OUT_BATCH(d, i, MI_BATCH_BUFFER_END); so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset; /* * Since we are sending length, we need to strictly conform to * all requirements. For Gen2 this must be a multiple of 8. */ so->aux_batch_size = ALIGN(so->aux_batch_size, 8); kunmap(page); ret = i915_gem_object_set_to_gtt_domain(so->vma->obj, false); if (ret) return ret; if (rodata->reloc[reloc_index] != -1) { DRM_ERROR("only %d relocs resolved\n", reloc_index); return -EINVAL; } return 0; err_out: kunmap(page); return ret; }