void vBSP430platformInitialize_ni (void)
{
int crystal_ok = 0;
(void)crystal_ok;
#if BSP430_PLATFORM_BOOT_DISABLE_WATCHDOG - 0
/* Hold off watchdog */
WDTCTL = WDTPW | WDTHOLD;
#endif /* configBSP430_CORE_SUPPORT_WATCHDOG */
#if (BSP430_PLATFORM_BOOT_CONFIGURE_LEDS - 0) && (BSP430_LED - 0)
vBSP430ledInitialize_ni();
#endif /* BSP430_PLATFORM_BOOT_CONFIGURE_LEDS */
#if BSP430_PLATFORM_BOOT_CONFIGURE_LFXT1 - 0
/* Enable XT1 functions and clock */
crystal_ok = iBSP430clockConfigureLFXT1_ni(1, (BSP430_PLATFORM_BOOT_LFXT1_DELAY_SEC * BSP430_CLOCK_PUC_MCLK_HZ) / BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES);
#endif /* BSP430_PLATFORM_BOOT_CONFIGURE_LFXT1 */
#if BSP430_PLATFORM_BOOT_CONFIGURE_CLOCKS - 0
iBSP430clockConfigureACLK_ni(BSP430_PLATFORM_BOOT_ACLKSRC);
ulBSP430clockConfigureMCLK_ni(BSP430_CLOCK_NOMINAL_MCLK_HZ);
iBSP430clockConfigureSMCLKDividingShift_ni(BSP430_CLOCK_NOMINAL_SMCLK_DIVIDING_SHIFT);
#if configBSP430_CORE_DISABLE_FLL - 0
__bis_status_register(SCG0);
#endif /* configBSP430_CORE_DISABLE_FLL */
#endif /* BSP430_PLATFORM_BOOT_CONFIGURE_CLOCKS */
#if BSP430_UPTIME - 0
vBSP430uptimeStart_ni();
#endif /* BSP430_UPTIME */
}
unsigned long
ulBSP430clockConfigureMCLK_ni (unsigned long mclk_Hz)
{
unsigned int flld = 0;
unsigned int fn_x = 0;
int dcoplus = 0;
unsigned int dcoclk_xt1 = (mclk_Hz + BSP430_CLOCK_NOMINAL_XT1CLK_HZ / 2) / BSP430_CLOCK_NOMINAL_XT1CLK_HZ;
/* Convert a value in MHz to the same value in ticks of LXFT1 */
#define MHZ_TO_XT1(_n) (((_n)*1000000UL) / BSP430_CLOCK_NOMINAL_XT1CLK_HZ)
/* Gross selection of DCO range. We select the range if the target
* frequency is above the midpoint of the previous range. */
if (MHZ_TO_XT1(26/2) < dcoclk_xt1) {
fn_x = FN_8;
} else if (MHZ_TO_XT1(17/2) < dcoclk_xt1) {
fn_x = FN_4;
} else if (MHZ_TO_XT1(12/2) < dcoclk_xt1) {
fn_x = FN_3;
} else if (MHZ_TO_XT1(6/2) < dcoclk_xt1) {
fn_x = FN_2;
}
#undef MHZ_TO_XT1
/* Need a divider if multiplier is too large. */
while (FLL_N_MASK < (dcoclk_xt1 - 1)) {
dcoplus = 1;
++flld;
dcoclk_xt1 /= 2;
}
(void)iBSP430clockConfigureLFXT1_ni(1, -1);
if (dcoplus) {
FLL_CTL0 |= DCOPLUS;
}
SCFQCTL = dcoclk_xt1 - 1;
SCFI0 = (flld * FLLD0) | fn_x;
/* Clear all the oscillator faults and spin until DCO stabilized. */
do {
BSP430_CLOCK_CLEAR_FAULTS_NI();
BSP430_CORE_WATCHDOG_CLEAR();
/* Conservatively assume a 32 MHz clock */
BSP430_CORE_DELAY_CYCLES(32 * BSP430_CLOCK_FAULT_RECHECK_DELAY_US);
} while (BSP430_FLLPLUS_DCO_IS_FAULTED_NI());
return ulBSP430clockMCLK_Hz_ni();
}
