static struct ia64_pal_retval pal_register_info(struct kvm_vcpu *vcpu)
{
struct ia64_pal_retval result = {0, 0, 0, 0};
long in0, in1, in2, in3;
kvm_get_pal_call_data(vcpu, &in0, &in1, &in2, &in3);
result.status = ia64_pal_register_info(in1, &result.v1, &result.v2);
return result;
}
static int
register_info(char *page)
{
char *p = page;
u64 reg_info[2];
u64 info;
unsigned long phys_stacked;
pal_hints_u_t hints;
unsigned long iregs, dregs;
char *info_type[]={
"Implemented AR(s)",
"AR(s) with read side-effects",
"Implemented CR(s)",
"CR(s) with read side-effects",
};
for(info=0; info < 4; info++) {
if (ia64_pal_register_info(info, ®_info[0], ®_info[1]) != 0) return 0;
p += sprintf(p, "%-32s : ", info_type[info]);
p = bitregister_process(p, reg_info, 128);
p += sprintf(p, "\n");
}
if (ia64_pal_rse_info(&phys_stacked, &hints) == 0) {
p += sprintf(p,
"RSE stacked physical registers : %ld\n"
"RSE load/store hints : %ld (%s)\n",
phys_stacked, hints.ph_data,
hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)");
}
if (ia64_pal_debug_info(&iregs, &dregs))
return 0;
p += sprintf(p,
"Instruction debug register pairs : %ld\n"
"Data debug register pairs : %ld\n", iregs, dregs);
return p - page;
}
