/* * Iキャッシュを停止 */ void icache_disable(void) { uint32_t bits; CP15_CONTROL_READ(bits); bits &= ~CP15_CONTROL_I_BIT; CP15_CONTROL_WRITE(bits); icache_invalidate(); }
/* * Iキャッシュの開始 */ void icache_enable(void) { uint32_t bits; CP15_CONTROL_READ(bits); /* * すでに有効ならリターン */ if(bits & CP15_CONTROL_I_BIT){ return; } icache_invalidate(); bits |= CP15_CONTROL_I_BIT; CP15_CONTROL_WRITE(bits); }
/** * ls1046a_esdhc_start_image - Load and start a 2nd stage from the ESDHC controller * * This loads and starts a 2nd stage barebox from an SD card and starts it. We * assume the image has been generated with scripts/pblimage.c which puts the * second stage to an offset of 128KiB in the image. * * Return: If successful, this function does not return. A negative error * code is returned when this function fails. */ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2) { int ret; uint32_t val; struct esdhc esdhc = { .regs = IOMEM(0x01560000), .is_be = true, }; unsigned long sdram = 0x80000000; void (*barebox)(unsigned long, unsigned long, unsigned long) = (void *)(sdram + LS1046A_SD_IMAGE_OFFSET); /* * The ROM leaves us here with a clock frequency of around 400kHz. Speed * this up a bit. FIXME: The resulting frequency has not yet been verified * to work on all cards. */ val = esdhc_read32(&esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET); val &= ~0x0000fff0; val |= (8 << 8) | (3 << 4); esdhc_write32(&esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val); esdhc_write32(&esdhc, ESDHC_DMA_SYSCTL, ESDHC_SYSCTL_DMA_SNOOP); ret = esdhc_read_blocks(&esdhc, (void *)sdram, ALIGN(barebox_image_size + LS1046A_SD_IMAGE_OFFSET, 512)); if (ret) { pr_err("%s: reading blocks failed with: %d\n", __func__, ret); return ret; } icache_invalidate(); printf("Starting barebox\n"); barebox(r0, r1, r2); return -EINVAL; }