/* Initilize dm9000 board */ static void dmfe_init_dm9000(struct net_device *dev) { board_info_t *db = (board_info_t *) dev->priv; DMFE_DBUG(0, "dmfe_init_dm9000()", 0); /* set the internal PHY power-on, GPIOs normal, and wait 2ms */ iow(db, 0x1F, 0); /* GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY */ udelay(20); /* wait 2ms for PHY power-on ready */ /* do a software reset and wait 20us */ iow(db, DM9000_NCR, 3); udelay(20); /* wait 20us at least for software reset ok */ iow(db, 0, 3); /* NCR (reg_00h) bit[0] RST=1 & Loopback=1, * reset on. Added by SPenser */ udelay(20); /* wait 20us at least for software reset ok */ // Marked by Spenser /* set GPIO0=1 then GPIO0=0 to turn off and on the internal PHY */ iow(db, 0x1F, 1); /* GPR (reg_1Fh) bit[0] GPIO0=1 turn-off PHY */ iow(db, 0x1F, 0); /* GPR (reg_1Fh) bit[0] GPIO0=0 activate PHY */ udelay(1000); /* wait 4ms linking PHY (AUTO sense) if RX/TX */ udelay(1000); udelay(1000); udelay(1000); /* I/O mode */ db->io_mode = ior(db, 0xfe) >> 6; /* ISR bit7:6 keeps I/O mode */ /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ identify_nic(db); /* Set PHY */ db->op_mode = media_mode; set_PHY_mode(db); /* Init needed register value */ db->reg0 = DM9000_NCR; if ((db->nic_type != FASTETHER_NIC) && (db->op_mode & DM9000_1M_HPNA)) db->reg0 |= DM9000_EXT_MII; /* User passed argument */ db->reg5 = reg5; db->reg8 = reg8; db->reg9 = reg9; db->rega = rega; /* Program operating register */ iow(db, 0x00, 0x08); iow(db, 0x02, 0); /* TX Polling clear */ iow(db, 0x2f, 0); /* Special Mode */ iow(db, 0x01, 0x2c); /* clear TX status */ iow(db, 0xfe, 0x0f); /* Clear interrupt status */ iow(db, 0x08, 0x37); iow(db, 0x09, 0x38); /* Flow control: High/Low water */ iow(db, 0x0a, 0x29); /* flow control */ /* Set address filter table */ dm9000_hash_table(dev); /* Activate DM9000 */ iow(db, 0x05, db->reg5 | 1); /* RX enable */ iow(db, 0xff, DM9000_REGFF); /* Enable TX/RX interrupt mask */ /* Init Driver variable */ db->link_failed = 1; db->tx_pkt_cnt = 0; db->queue_pkt_len = 0; dev->trans_start = 0; netif_carrier_on(dev); spin_lock_init(&db->lock); }
/* Initilize dm9000 board */ int eth_init(bd_t * bd) { int i, oft; DM9000_DBG("eth_init()\n"); /* RESET device */ dm9000_reset(); dm9000_probe(); /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ identify_nic(); /* GPIO0 on pre-activate PHY */ DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */ /* Set PHY */ set_PHY_mode(); /* Program operating register */ DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ /* Set Node address */ //HJ_start /* www.embedsky.net */ char *tmp = getenv("ethaddr"); char *end; for (i = 0; i < 6; i++) { bd->bi_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; if(tmp) tmp = (*end) ? end+1 : end; } //HJ_end /* www.embedsky.net */ printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]); for (i = 0, oft = 0x10; i < 6; i++, oft++) DM9000_iow(oft, bd->bi_enetaddr[i]); for (i = 0, oft = 0x16; i < 8; i++, oft++) DM9000_iow(oft, 0xff); /* read back mac, just to be sure */ for (i = 0, oft = 0x10; i < 6; i++, oft++) DM9000_DBG("%02x:", DM9000_ior(oft)); DM9000_DBG("\n"); /* Activate DM9000 */ DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ return 0; }
/* Initilize dm9000 board */ int eth_init(bd_t * bd) { int i, oft, lnk; DM9000_DBG("eth_init()\n"); /* RESET device */ dm9000_reset(); dm9000_probe(); /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ identify_nic(); /* GPIO0 on pre-activate PHY */ DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */ /* Set PHY */ set_PHY_mode(); /* Program operating register */ DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ /* Set Node address */ // for (i = 0; i < 6; i++) //raymanfeng- // ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]); for (i = 0, oft = 0x10; i < 6; i++, oft++) DM9000_iow(oft, bd->bi_enetaddr[i]); for (i = 0, oft = 0x16; i < 8; i++, oft++) DM9000_iow(oft, 0xff); /* read back mac, just to be sure */ for (i = 0, oft = 0x10; i < 6; i++, oft++) DM9000_DBG("%02x:", DM9000_ior(oft)); DM9000_DBG("\n"); /* Activate DM9000 */ DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ /* //raymanfeng- i = 0; while (!(phy_read(1) & 0x20)) { // autonegation complete bit udelay(1000); i++; if (i == 10000) { printf("could not establish link\n"); return 0; } } // see what we've got lnk = phy_read(17) >> 12; printf("operating at "); switch (lnk) { case 1: printf("10M half duplex "); break; case 2: printf("10M full duplex "); break; case 4: printf("100M half duplex "); break; case 8: printf("100M full duplex "); break; default: printf("unknown: %d ", lnk); break; } printf("mode\n"); */ return 0; }