void main(void)
{
int i = 0;
volatile uint16_t dataA = 0;
volatile uint16_t dataB = 0;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
/* Select OCP_CLK as IEP clock source */
CT_CFG.IEPCLK_bit.OCP_EN = 0x1;
iep_timer_config();
intc_config();
CT_IEP.TMR_GLB_CFG_bit.CNT_EN = 0x1;
/* Setting PRU1 GPO Clk Dividers to 12.5 and 2 to get 8 MHz CLK */
CT_CFG.GPCFG1_bit.PRU1_GPO_DIV0 = 0x17;
CT_CFG.GPCFG1_bit.PRU1_GPO_DIV1 = 0x02;
/* Init the configure registers and put them in shift out mode */
CT_CFG.GPCFG1_bit.PRU1_GPO_MODE = PRU1_GPO_MODE_SERIAL;
/* Init PRU1 GPO to 0 */
__R30 = 0x0;
SH0_Load(0);
SH1_Load(0);
/* Enable PRU1 GPO shift out */
__R30 |= SHIFT_ENABLE_FLAG << SHIFT_ENABLE_SHIFT;
while (1) {
for (i = 0; i < 0xFF; i++) {
/* Poll until R31.30 is set */
do {
while ((__R31 & 0x40000000) == 0) {
}
/* Verify that the IEP is the source of the interrupt */
} while (CT_INTC.HIPIR0 != PRU_IEP_EVT);
/* Clear Compare0 status */
CT_IEP.TMR_CMP_STS = 0x1;
__delay_cycles(2);
/* Clear the status of the interrupt */
CT_INTC.SECR0 = (1 << PRU_IEP_EVT);
/* Format sine wave data for DAC */
dataA = DAC_Cmd(DAC_A_ADDRESS, WRITE_NO_UPDATE, SineRaw[i]);
/* Swap data endian from LSB first to MSB first per DAC format*/
dataA = Endian_Swap(dataA);
/* Load data into Shadow Register 0 */
SH0_Load(dataA);
while (!(CT_CFG.GPCFG1 & PRU1_GPO_SH_SEL_MASK));
/* Wait for SH Flag to indicate SH0 being output */
while ((CT_CFG.GPCFG1 & PRU1_GPO_SH_SEL_MASK));
/* Generate sync signal */
__R30 |= 0x0004;
__delay_cycles(2);
__R30 &= ~0x4;
/* Format sine wave data for DAC */
dataB = DAC_Cmd(DAC_B_ADDRESS, WRITE_UPDATE, SineRaw[i]);
/* Swap data endian from LSB first to MSB first per DAC format */
dataB = Endian_Swap(dataB);
/* Load data into Shadow Register 1 */
SH1_Load(dataB);
/* Wait for SH Flag to indicate SH1 being output */
while (!(CT_CFG.GPCFG1 & PRU1_GPO_SH_SEL_MASK));
/* Generate sync signal */
__R30 |= 0x0004;
__delay_cycles(2);
__R30 &= ~0x4;
}
}
}
void main(){
unsigned int status, crc_calc, i, j = 0;
char bit_val, byte_val = 0;
/* Initialize TEMP_SENSOR_BUF to 0 */
memset(TEMP_SENSOR_BUF, 0, 9);
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
/* Configure IEP timer */
iep_timer_config();
/* Configure IEP digio */
iep_digio_config();
CT_IEP.DIGIO_DATA_OUT_EN = OUT_1WIRE;
/* Interrupt Master PRU */
PRU_SLAVE_MASTER_EVT_TRIGGER;
while(1){
/* Detect Master PRU interrupt: Read Temp */
while((__R31 & 0x40000000) == 0){
}
/* Clear system event */
CT_INTC.SECR0 = (1 << PRU_MASTER_SLAVE_EVT);
/* Issue Convert T command to sensor */
init();
write_cmd(SKIP_ROM);
write_cmd(CONVERT_T);
while(status == 0){
status = read();
}
status = 0;
/* Issue Read Scratchpad command to sensor */
init();
write_cmd(SKIP_ROM);
write_cmd(READ_SCRATCHPAD);
crc_calc = 0;
/* Read sensor scratchpad's 9 bytes of data */
for(i=0; i < 9; i++){
byte_val = 0;
/* Read 8 bits per byte */
for(j=0; j < 8; j++){
bit_val = read();
byte_val = byte_val | (bit_val << j);
}
/* Store each byte of data in memory (PRU Shared RAM) */
TEMP_SENSOR_BUF[i] = byte_val;
/* Calculate CRC after each byte of data read */
crc_calc = CRC_BYTE_ARRAY[crc_calc ^ byte_val];
}
/* Compare CRC values */
/* If CRC value matches, interrupt Master that temp value is ready */
if(crc_calc == 0x0){
PRU_SLAVE_MASTER_EVT_TRIGGER;
}
/* If CRC value does not match, re-sample temp */
if(crc_calc != 0x0){
PRU_MASTER_SLAVE_EVT_TRIGGER;
}
}
}
