static int eukrea_cpuimx27_devices_init(void) { char *envdev = "no"; int i; unsigned int mode[] = { PD0_AIN_FEC_TXD0, PD1_AIN_FEC_TXD1, PD2_AIN_FEC_TXD2, PD3_AIN_FEC_TXD3, PD4_AOUT_FEC_RX_ER, PD5_AOUT_FEC_RXD1, PD6_AOUT_FEC_RXD2, PD7_AOUT_FEC_RXD3, PD8_AF_FEC_MDIO, PD9_AIN_FEC_MDC | GPIO_PUEN, PD10_AOUT_FEC_CRS, PD11_AOUT_FEC_TX_CLK, PD12_AOUT_FEC_RXD0, PD13_AOUT_FEC_RX_DV, PD14_AOUT_FEC_RX_CLK, PD15_AOUT_FEC_COL, PD16_AIN_FEC_TX_ER, PF23_AIN_FEC_TX_EN, PD17_PF_I2C_DATA, PD18_PF_I2C_CLK, #ifdef CONFIG_DRIVER_SERIAL_IMX PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, PE14_PF_UART1_CTS, PE15_PF_UART1_RTS, #endif #ifdef CONFIG_DRIVER_VIDEO_IMX PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2, PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6, PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10, PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14, PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA28_PF_HSYNC, PA29_PF_VSYNC, PA31_PF_OE_ACD, GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT, GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT, #endif }; /* configure 16 bit nor flash on cs0 */ CS0U = 0x00008F03; CS0L = 0xA0330D01; CS0A = 0x002208C0; /* initialize gpios */ for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0); #ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB add_cfi_flash_device(-1, 0xC2000000, 32 * 1024 * 1024, 0); #endif imx27_add_nand(&nand_info); PCCR0 |= PCCR0_I2C1_EN; i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); imx27_add_i2c0(NULL); devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); protect_file("/dev/env0", 1); envdev = "NOR"; printf("Using environment in %s Flash\n", envdev); #ifdef CONFIG_DRIVER_VIDEO_IMX imx_add_fb((void *)0x10021000, &eukrea_cpuimx27_fb_data); gpio_direction_output(GPIO_PORTE | 5, 0); gpio_set_value(GPIO_PORTE | 5, 1); gpio_direction_output(GPIO_PORTA | 25, 0); gpio_set_value(GPIO_PORTA | 25, 1); #endif armlinux_set_bootparams((void *)0xa0000100); armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX27); return 0; }
static int pcm038_devices_init(void) { int i; char *envdev; unsigned int mode[] = { PD0_AIN_FEC_TXD0, PD1_AIN_FEC_TXD1, PD2_AIN_FEC_TXD2, PD3_AIN_FEC_TXD3, PD4_AOUT_FEC_RX_ER, PD5_AOUT_FEC_RXD1, PD6_AOUT_FEC_RXD2, PD7_AOUT_FEC_RXD3, PD8_AF_FEC_MDIO, PD9_AIN_FEC_MDC | GPIO_PUEN, PD10_AOUT_FEC_CRS, PD11_AOUT_FEC_TX_CLK, PD12_AOUT_FEC_RXD0, PD13_AOUT_FEC_RX_DV, PD14_AOUT_FEC_RX_CLK, PD15_AOUT_FEC_COL, PD16_AIN_FEC_TX_ER, PF23_AIN_FEC_TX_EN, PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, PE14_PF_UART1_CTS, PE15_PF_UART1_RTS, PD25_PF_CSPI1_RDY, GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT, PD29_PF_CSPI1_SCLK, PD30_PF_CSPI1_MISO, PD31_PF_CSPI1_MOSI, /* display */ PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2, PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6, PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10, PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14, PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA24_PF_REV, PA25_PF_CLS, PA26_PF_PS, PA27_PF_SPL_SPR, PA28_PF_HSYNC, PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD, /* USB host 2 */ PA0_PF_USBH2_CLK, PA1_PF_USBH2_DIR, PA2_PF_USBH2_DATA7, PA3_PF_USBH2_NXT, PA4_PF_USBH2_STP, PD19_AF_USBH2_DATA4, PD20_AF_USBH2_DATA3, PD21_AF_USBH2_DATA6, PD22_AF_USBH2_DATA0, PD23_AF_USBH2_DATA2, PD24_AF_USBH2_DATA1, PD26_AF_USBH2_DATA5, /* I2C1 */ PD17_PF_I2C_DATA | GPIO_PUEN, PD18_PF_I2C_CLK, /* I2C2 */ PC5_PF_I2C2_SDA, PC6_PF_I2C2_SCL, }; /* configure 16 bit nor flash on cs0 */ CS0U = 0x22C2CF00; CS0L = 0x75000D01; CS0A = 0x00000900; /* configure SRAM on cs1 */ CS1U = 0x0000d843; CS1L = 0x22252521; CS1A = 0x22220a00; /* configure SJA1000 on cs4 */ CS4U = 0x0000DCF6; CS4L = 0x444A0301; CS4A = 0x44443302; /* initizalize gpios */ for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); PCCR0 |= PCCR0_CSPI1_EN; PCCR1 |= PCCR1_PERCLK2_EN; gpio_direction_output(GPIO_PORTD | 28, 0); gpio_set_value(GPIO_PORTD | 28, 0); spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); imx27_add_spi0(&pcm038_spi_0_data); add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0); imx27_add_nand(&nand_info); imx27_add_fb(&pcm038_fb_data); PCCR0 |= PCCR0_I2C1_EN | PCCR0_I2C2_EN; imx27_add_i2c0(NULL); imx27_add_i2c1(NULL); #ifdef CONFIG_USB pcm038_usbh_init(); add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL); #endif /* Register the fec device after the PLL re-initialisation * as the fec depends on the (now higher) ipg clock */ imx27_add_fec(&fec_info); switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) { case GPCR_BOOT_8BIT_NAND_2k: case GPCR_BOOT_16BIT_NAND_2k: case GPCR_BOOT_16BIT_NAND_512: case GPCR_BOOT_8BIT_NAND_512: devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); envdev = "NAND"; break; default: devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); protect_file("/dev/env0", 1); envdev = "NOR"; } printf("Using environment in %s Flash\n", envdev); armlinux_set_bootparams((void *)0xa0000100); armlinux_set_architecture(MACH_TYPE_PCM038); return 0; }
static int pcm038_devices_init(void) { int i; u64 uid = 0; char *envdev; long sram_size; unsigned int mode[] = { /* FEC */ PD0_AIN_FEC_TXD0, PD1_AIN_FEC_TXD1, PD2_AIN_FEC_TXD2, PD3_AIN_FEC_TXD3, PD4_AOUT_FEC_RX_ER, PD5_AOUT_FEC_RXD1, PD6_AOUT_FEC_RXD2, PD7_AOUT_FEC_RXD3, PD8_AF_FEC_MDIO, PD9_AIN_FEC_MDC | GPIO_PUEN, PD10_AOUT_FEC_CRS, PD11_AOUT_FEC_TX_CLK, PD12_AOUT_FEC_RXD0, PD13_AOUT_FEC_RX_DV, PD14_AOUT_FEC_RX_CLK, PD15_AOUT_FEC_COL, PD16_AIN_FEC_TX_ER, PF23_AIN_FEC_TX_EN, PCM038_GPIO_FEC_RST | GPIO_GPIO | GPIO_OUT, /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, PE14_PF_UART1_CTS, PE15_PF_UART1_RTS, /* CSPI1 */ PD25_PF_CSPI1_RDY, PD29_PF_CSPI1_SCLK, PD30_PF_CSPI1_MISO, PD31_PF_CSPI1_MOSI, PCM038_GPIO_SPI_CS0 | GPIO_GPIO | GPIO_OUT, #ifdef CONFIG_MACH_PCM970_BASEBOARD PCM970_GPIO_SPI_CS1 | GPIO_GPIO | GPIO_OUT, #endif /* Display */ PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2, PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6, PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10, PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14, PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA24_PF_REV, PA25_PF_CLS, PA26_PF_PS, PA27_PF_SPL_SPR, PA28_PF_HSYNC, PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD, /* USB OTG */ PC7_PF_USBOTG_DATA5, PC8_PF_USBOTG_DATA6, PC9_PF_USBOTG_DATA0, PC10_PF_USBOTG_DATA2, PC11_PF_USBOTG_DATA1, PC12_PF_USBOTG_DATA4, PC13_PF_USBOTG_DATA3, PE0_PF_USBOTG_NXT, PCM038_GPIO_OTG_STP | GPIO_GPIO | GPIO_OUT, PE2_PF_USBOTG_DIR, PE24_PF_USBOTG_CLK, PE25_PF_USBOTG_DATA7, /* I2C1 */ PD17_PF_I2C_DATA | GPIO_PUEN, PD18_PF_I2C_CLK, /* I2C2 */ PC5_PF_I2C2_SDA, PC6_PF_I2C2_SCL, }; /* configure 16 bit nor flash on cs0 */ imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900); /* configure SRAM on cs1 */ imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); /* SRAM can be up to 2MiB */ sram_size = get_ram_size((ulong *)MX27_CS1_BASE_ADDR, SZ_2M); if (sram_size) add_mem_device("ram1", MX27_CS1_BASE_ADDR, sram_size, IORESOURCE_MEM_WRITEABLE); /* initizalize gpios */ for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); imx27_add_spi0(&pcm038_spi_0_data); pcm038_power_init(); add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); imx27_add_nand(&nand_info); imx27_add_fb(&pcm038_fb_data); imx27_add_i2c0(NULL); imx27_add_i2c1(NULL); /* Register the fec device after the PLL re-initialisation * as the fec depends on the (now higher) ipg clock */ gpio_set_value(PCM038_GPIO_FEC_RST, 1); imx27_add_fec(&fec_info); /* Apply delay for STP line to stop ULPI */ gpio_direction_output(PCM038_GPIO_OTG_STP, 1); mdelay(1); imx_gpio_mode(PE1_PF_USBOTG_STP); imx27_add_usbotg(&pcm038_otg_pdata); switch (bootsource_get()) { case BOOTSOURCE_NAND: devfs_add_partition("nand0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); envdev = "NAND"; break; default: devfs_add_partition("nor0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0"); protect_file("/dev/env0", 1); envdev = "NOR"; } pr_notice("Using environment in %s Flash\n", envdev); if (imx_iim_read(1, 0, &uid, 6) == 6) armlinux_set_serial(uid); armlinux_set_bootparams((void *)0xa0000100); armlinux_set_architecture(MACH_TYPE_PCM038); return 0; }