static int
temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS)
{
struct imx6_anatop_softc *sc = arg1;
int err;
uint32_t temp;
temp = sc->temp_throttle_val + TZ_ZEROC;
err = sysctl_handle_int(oidp, &temp, 0, req);
if (temp < TZ_ZEROC)
return (ERANGE);
temp -= TZ_ZEROC;
if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val)
return (err);
/* Value changed, update counts in softc and hardware. */
sc->temp_throttle_val = temp;
sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val);
sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100);
imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR,
IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK);
imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET,
(sc->temp_throttle_trigger_cnt <<
IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT));
return (err);
}
static void
initialize_tempmon(struct imx6_anatop_softc *sc)
{
uint32_t cal;
struct sysctl_ctx_list *ctx;
/*
* Fetch calibration data: a sensor count at room temperature (25C),
* a sensor count at a high temperature, and that temperature
*/
cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1);
sc->temp_room_cnt = (cal & 0xFFF00000) >> 20;
sc->temp_high_cnt = (cal & 0x000FFF00) >> 8;
sc->temp_high_val = (cal & 0x000000FF) * 10;
/*
* Throttle to a lower cpu freq at 10C below the "hot" temperature, and
* reset back to max cpu freq at 5C below the trigger.
*/
sc->temp_throttle_val = sc->temp_high_val - 100;
sc->temp_throttle_trigger_cnt =
temp_to_count(sc, sc->temp_throttle_val);
sc->temp_throttle_reset_cnt =
temp_to_count(sc, sc->temp_throttle_val - 50);
/*
* Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set
* the throttle count, and begin making measurements.
*/
imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800);
imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0,
(sc->temp_throttle_trigger_cnt <<
IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) |
IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE);
/*
* XXX Note that the alarm-interrupt feature isn't working yet, so
* we'll use a callout handler to check at 10Hz. Make sure we have an
* initial temperature reading before starting up the callouts so we
* don't get a bogus reading of zero.
*/
while (sc->temp_last_cnt == 0)
temp_update_count(sc);
sc->temp_throttle_delay = 100 * SBT_1MS;
callout_init(&sc->temp_throttle_callout, 0);
callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
0, tempmon_throttle_check, sc, 0);
ctx = device_get_sysctl_ctx(sc->dev);
SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0,
temp_sysctl_handler, "IK", "Current die temperature");
SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc,
0, temp_throttle_sysctl_handler, "IK",
"Throttle CPU when exceeding this temperature");
}
static void
cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op)
{
uint32_t corediv, plldiv, timeout, wrk32;
/* If increasing the frequency, we must first increase the voltage. */
if (op->mhz > sc->cpu_curmhz) {
vdd_set(sc, op->mv);
}
/*
* I can't find a documented procedure for changing the ARM PLL divisor,
* but some trial and error came up with this:
* - Set the bypass clock source to REF_CLK_24M (source #0).
* - Set the PLL into bypass mode; cpu should now be running at 24mhz.
* - Change the divisor.
* - Wait for the LOCK bit to come on; it takes ~50 loop iterations.
* - Turn off bypass mode; cpu should now be running at the new speed.
*/
cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv);
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK);
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET,
IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM);
wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
wrk32 |= plldiv;
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32);
timeout = 10000;
while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0)
if (--timeout == 0)
panic("imx6_set_cpu_clock(): PLL never locked");
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
imx_ccm_set_cacrr(corediv);
/* If lowering the frequency, it is now safe to lower the voltage. */
if (op->mhz < sc->cpu_curmhz)
vdd_set(sc, op->mv);
sc->cpu_curmhz = op->mhz;
/* Tell the mpcore timer that its frequency has changed. */
arm_tmr_change_frequency(
cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2);
}
static void
vdd_set(struct imx6_anatop_softc *sc, int mv)
{
int newtarg, oldtarg;
uint32_t delay, pmureg;
static boolean_t init_done = false;
/*
* The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM
* can't be more than 50mV above or 200mV below them. For now to keep
* things simple we set all three to the same value.
*/
pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE);
oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK;
/* Convert mV to target value. Clamp target to valid range. */
if (mv < 725)
newtarg = 0x00;
else if (mv > 1450)
newtarg = 0x1F;
else
newtarg = (mv - 700) / 25;
/*
* The first time through the 3 voltages might not be equal so use a
* long conservative delay. After that we need to delay 3uS for every
* 25mV step upward. No need to delay at all when lowering.
*/
if (init_done) {
if (newtarg == oldtarg)
return;
else if (newtarg > oldtarg)
delay = (newtarg - oldtarg) * 3;
else
delay = 0;
} else {
delay = 700 / 25 * 3;
init_done = true;
}
/*
* Make the change and wait for it to take effect.
*/
pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK |
IMX6_ANALOG_PMU_REG1_TARG_MASK |
IMX6_ANALOG_PMU_REG2_TARG_MASK);
pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT;
pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT;
pmureg |= newtarg << IMX6_ANALOG_PMU_REG2_TARG_SHIFT;
imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg);
DELAY(delay);
sc->cpu_curmv = newtarg * 25 + 700;
}
void
imx_ccm_usbphy_enable(device_t _phydev)
{
/*
* XXX Which unit?
* Right now it's not clear how to figure from fdt data which phy unit
* we're supposed to operate on. Until this is worked out, just enable
* both PHYs.
*/
#if 0
int phy_num, regoff;
phy_num = 0; /* XXX */
switch (phy_num) {
case 0:
regoff = 0;
break;
case 1:
regoff = 0x10;
break;
default:
device_printf(ccm_sc->dev, "Bad PHY number %u,\n",
phy_num);
return;
}
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff,
IMX6_ANALOG_CCM_PLL_USB_ENABLE |
IMX6_ANALOG_CCM_PLL_USB_POWER |
IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
#else
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0,
IMX6_ANALOG_CCM_PLL_USB_ENABLE |
IMX6_ANALOG_CCM_PLL_USB_POWER |
IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10,
IMX6_ANALOG_CCM_PLL_USB_ENABLE |
IMX6_ANALOG_CCM_PLL_USB_POWER |
IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
#endif
}
uint32_t
pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd)
{
int reg;
/*
* Audio PLL (PLL4).
* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
*/
reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE);
reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \
IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg);
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn);
imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd);
return (0);
}
static int
imx6_anatop_attach(device_t dev)
{
struct imx6_anatop_softc *sc;
int err;
sc = device_get_softc(dev);
sc->dev = dev;
/* Allocate bus_space resources. */
if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
device_printf(dev, "Cannot allocate resources\n");
err = ENXIO;
goto out;
}
err = bus_setup_intr(dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE,
tempmon_intr, NULL, sc, &sc->temp_intrhand);
if (err != 0)
goto out;
SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
OID_AUTO, "cpu_voltage", CTLFLAG_RD,
&sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
imx6_anatop_sc = sc;
/*
* Other code seen on the net sets this SELFBIASOFF flag around the same
* time the temperature sensor is set up, although it's unclear how the
* two are related (if at all).
*/
imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET,
IMX6_ANALOG_PMU_MISC0_SELFBIASOFF);
cpufreq_initialize(sc);
initialize_tempmon(sc);
if (bootverbose) {
device_printf(sc->dev, "CPU %uMHz @ %umV\n", sc->cpu_curmhz,
sc->cpu_curmv);
}
err = 0;
out:
if (err != 0) {
bus_release_resources(dev, imx6_anatop_spec, sc->res);
}
return (err);
}
static int
imx6_anatop_attach(device_t dev)
{
struct imx6_anatop_softc *sc;
int err;
sc = device_get_softc(dev);
sc->dev = dev;
/* Allocate bus_space resources. */
if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
device_printf(dev, "Cannot allocate resources\n");
err = ENXIO;
goto out;
}
sc->intr_setup_hook.ich_func = intr_setup;
sc->intr_setup_hook.ich_arg = sc;
config_intrhook_establish(&sc->intr_setup_hook);
SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
OID_AUTO, "cpu_voltage", CTLFLAG_RD,
&sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
imx6_anatop_sc = sc;
/*
* Other code seen on the net sets this SELFBIASOFF flag around the same
* time the temperature sensor is set up, although it's unclear how the
* two are related (if at all).
*/
imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET,
IMX6_ANALOG_PMU_MISC0_SELFBIASOFF);
/*
* Some day, when we're ready to deal with the actual anatop regulators
* that are described in fdt data as children of this "bus", this would
* be the place to invoke a simplebus helper routine to instantiate the
* children from the fdt data.
*/
err = 0;
out:
if (err != 0) {
bus_release_resources(dev, imx6_anatop_spec, sc->res);
}
return (err);
}
static int
usbphy_attach(device_t dev)
{
struct usbphy_softc *sc;
int err, regoff, rid;
sc = device_get_softc(dev);
err = 0;
/* Allocate bus_space resources. */
rid = 0;
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res == NULL) {
device_printf(dev, "Cannot allocate memory resources\n");
err = ENXIO;
goto out;
}
/*
* XXX Totally lame way to get the unit number (but not quite as lame as
* adding an ad-hoc property to the fdt data). This works as long as
* this driver is used for imx6 only.
*/
const uint32_t PWD_PHY1_REG_PHYSADDR = 0x020c9000;
if (BUS_SPACE_PHYSADDR(sc->mem_res, 0) == PWD_PHY1_REG_PHYSADDR) {
sc->phy_num = 0;
regoff = 0;
} else {
sc->phy_num = 1;
regoff = 0x60;
}
/*
* Based on a note in the u-boot source code, disable charger detection
* to avoid degrading the differential signaling on the DP line. Note
* that this disables (by design) both charger detection and contact
* detection, because of the screwball mix of active-high and active-low
* bits in this register.
*/
imx6_anatop_write_4(IMX6_ANALOG_USB1_CHRG_DETECT + regoff,
IMX6_ANALOG_USB_CHRG_DETECT_N_ENABLE |
IMX6_ANALOG_USB_CHRG_DETECT_N_CHK_CHRG);
imx6_anatop_write_4(IMX6_ANALOG_USB1_CHRG_DETECT + regoff,
IMX6_ANALOG_USB_CHRG_DETECT_N_ENABLE |
IMX6_ANALOG_USB_CHRG_DETECT_N_CHK_CHRG);
/* XXX Configure the overcurrent detection here. */
/*
* Turn on the phy clocks.
*/
imx_ccm_usbphy_enable(dev);
/*
* Set the software reset bit, then clear both it and the clock gate bit
* to bring the device out of reset with the clock running.
*/
bus_write_4(sc->mem_res, CTRL_SET_REG, CTRL_SFTRST);
bus_write_4(sc->mem_res, CTRL_CLR_REG, CTRL_SFTRST | CTRL_CLKGATE);
/* Power up: clear all bits in the powerdown register. */
bus_write_4(sc->mem_res, PWD_REG, 0);
err = 0;
out:
if (err != 0)
usbphy_detach(dev);
return (err);
}
static void
vdd_set(struct imx6_anatop_softc *sc, int mv)
{
int newtarg, newtargSoc, oldtarg;
uint32_t delay, pmureg;
static boolean_t init_done = false;
/*
* The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM
* can't be more than 50mV above or 200mV below them. We keep them the
* same except in the case of the lowest operating point, which is
* handled as a special case below.
*/
pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE);
oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK;
/* Convert mV to target value. Clamp target to valid range. */
if (mv < 725)
newtarg = 0x00;
else if (mv > 1450)
newtarg = 0x1F;
else
newtarg = (mv - 700) / 25;
/*
* The SOC voltage can't go below 1150mV, and thus because of the 200mV
* rule, the ARM voltage can't go below 950mV. The 950 is encoded in
* our oppt table, here we handle the SOC 1150 rule as a special case.
* (1150-700/25=18).
*/
newtargSoc = (newtarg < 18) ? 18 : newtarg;
/*
* The first time through the 3 voltages might not be equal so use a
* long conservative delay. After that we need to delay 3uS for every
* 25mV step upward; we actually delay 6uS because empirically, it works
* and the 3uS per step recommended by the docs doesn't (3uS fails when
* going from 400->1200, but works for smaller changes).
*/
if (init_done) {
if (newtarg == oldtarg)
return;
else if (newtarg > oldtarg)
delay = (newtarg - oldtarg) * 6;
else
delay = 0;
} else {
delay = (700 / 25) * 6;
init_done = true;
}
/*
* Make the change and wait for it to take effect.
*/
pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK |
IMX6_ANALOG_PMU_REG1_TARG_MASK |
IMX6_ANALOG_PMU_REG2_TARG_MASK);
pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT;
pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT;
pmureg |= newtargSoc << IMX6_ANALOG_PMU_REG2_TARG_SHIFT;
imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg);
DELAY(delay);
sc->cpu_curmv = newtarg * 25 + 700;
}
