static int imx53_silicon_revision(void)
{
void __iomem *rom = MX53_IROM_BASE_ADDR;
u32 rev;
u32 mx53_silicon_revision;
rev = readl(rom + SI_REV);
switch (rev) {
case 0x10:
mx53_silicon_revision = IMX_CHIP_REV_1_0;
break;
case 0x20:
mx53_silicon_revision = IMX_CHIP_REV_2_0;
break;
case 0x21:
mx53_silicon_revision = IMX_CHIP_REV_2_1;
break;
default:
mx53_silicon_revision = 0;
}
imx_set_silicon_revision("i.MX53", mx53_silicon_revision);
return 0;
}
int imx7_init(void)
{
const char *cputypestr;
void __iomem *src = IOMEM(MX7_SRC_BASE_ADDR);
imx7_init_lowlevel();
imx7_init_csu();
imx7_boot_save_loc();
psci_set_ops(&imx7_psci_ops);
switch (imx7_cpu_type()) {
case IMX7_CPUTYPE_IMX7D:
cputypestr = "i.MX7d";
break;
case IMX7_CPUTYPE_IMX7S:
cputypestr = "i.MX7s";
break;
default:
cputypestr = "unknown i.MX7";
break;
}
imx_set_silicon_revision(cputypestr, imx7_cpu_revision());
imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);
return 0;
}
static void imx35_silicon_revision(void)
{
uint32_t reg;
reg = readl(MX35_IIM_BASE_ADDR + IIM_SREV);
/* 0×00 = TO 1.0, First silicon */
reg += IMX_CHIP_REV_1_0;
imx_set_silicon_revision("i.MX35", reg & 0xFF);
}
int imx8mq_init(void)
{
void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
void __iomem *src = IOMEM(MX8MQ_SRC_BASE_ADDR);
uint32_t type = FIELD_GET(DIGPROG_MAJOR,
readl(anatop + MX8MQ_ANATOP_DIGPROG));
struct arm_smccc_res res;
const char *cputypestr;
imx8_boot_save_loc();
switch (type) {
case IMX8M_CPUTYPE_IMX8MQ:
cputypestr = "i.MX8MQ";
break;
default:
cputypestr = "unknown i.MX8M";
break;
};
imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision());
/*
* Reset reasons seem to be identical to that of i.MX7
*/
imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);
if (IS_ENABLED(CONFIG_ARM_SMCCC) &&
IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) {
arm_smccc_smc(FSL_SIP_BUILDINFO,
FSL_SIP_BUILDINFO_GET_COMMITHASH,
0, 0, 0, 0, 0, 0, &res);
pr_info("i.MX ARM Trusted Firmware: %s\n", (char *)&res.a0);
}
return 0;
}
int imx6_init(void)
{
const char *cputypestr;
u32 rev;
u32 mx6_silicon_revision;
imx6_init_lowlevel();
imx6_boot_save_loc((void *)MX6_SRC_BASE_ADDR);
rev = readl(MX6_ANATOP_BASE_ADDR + SI_REV);
switch (rev & 0xff) {
case 0x00:
mx6_silicon_revision = IMX_CHIP_REV_1_0;
break;
case 0x01:
mx6_silicon_revision = IMX_CHIP_REV_1_1;
break;
case 0x02:
mx6_silicon_revision = IMX_CHIP_REV_1_2;
break;
case 0x03:
mx6_silicon_revision = IMX_CHIP_REV_1_3;
break;
case 0x04:
mx6_silicon_revision = IMX_CHIP_REV_1_4;
break;
case 0x05:
mx6_silicon_revision = IMX_CHIP_REV_1_5;
break;
default:
mx6_silicon_revision = IMX_CHIP_REV_UNKNOWN;
}
switch (imx6_cpu_type()) {
case IMX6_CPUTYPE_IMX6Q:
cputypestr = "i.MX6 Quad";
break;
case IMX6_CPUTYPE_IMX6D:
cputypestr = "i.MX6 Dual";
break;
case IMX6_CPUTYPE_IMX6DL:
cputypestr = "i.MX6 DualLite";
break;
case IMX6_CPUTYPE_IMX6S:
cputypestr = "i.MX6 Solo";
break;
case IMX6_CPUTYPE_IMX6SX:
cputypestr = "i.MX6 SoloX";
break;
default:
cputypestr = "unknown i.MX6";
break;
}
imx_set_silicon_revision(cputypestr, mx6_silicon_revision);
return 0;
}
