MessageRemindForm::MessageRemindForm(QWidget *parent) :
QWidget(parent)
{
setupUi(this);
initSetting();
initData();
}
TreeWidgetComponent::TreeWidgetComponent(QWidget *parent) :
QTreeWidget(parent)
{
initSetting();
initData();
initGui();
}
Parameter_LED8x8_Form::Parameter_LED8x8_Form(const QRect rect, QWidget *parent)
: QWidget(parent)
, pParent_(parent)
, rect_(rect)
{
setupUi(this);
initSetting();
initGui();
}
UploadWaitForm::UploadWaitForm(const QRect &rect, QWidget *parent)
: QWidget(parent)
, pParent_(parent)
, rect_(rect)
, bError_(false)
, bDone_(false)
{
setupUi(this);
initSetting();
initData();
initGui();
}
int larb_reg_restore(int larb)
{
unsigned int regval,regval1,regval2;
unsigned int larb_base = gLarbBaseAddr[larb];
/*
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) );
M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) );
for(i=0; i<3; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
*/
//Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns
//Got to enable OSTD before engine starts
regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT);
regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0);
regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1);
if(0 == regval)
{
M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff);
}
else
{
SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2);
smi_dumpDebugMsg();
SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2);
}
if(0 == g_bInited)
{
initSetting();
g_bInited = 1;
SMIMSG("SMI init\n");
}
return 0;
}
//--------------------------------------------------------------
void ksdraw12129::init(){
ofDisableArbTex();
initSetting();
//绘制一个基本图形
mesh.addVertex(
ofPoint(0.0f,-141.0f));
mesh.addVertex(
ofPoint(141.0f,0.0f));
mesh.addVertex(
ofPoint(0.0f,141.0f));
mesh.addVertex(
ofPoint(-141.0f,0.0f));
mesh.addVertex(
ofPoint(0.0f,0));
mesh.addTexCoord(ofVec2f(0,1));
mesh.addTexCoord(ofVec2f(1,1));
mesh.addTexCoord(ofVec2f(0,1));
mesh.addTexCoord(ofVec2f(1,1));
mesh.addTexCoord(ofVec2f(0.5,0.5));
ofIndexType ids[12] =
{
4,0,1,
4,1,2,
4,2,3,
4,3,0,
};
mesh.addIndices(ids,12);
//gui->addLabel("ksDraw");
speed1Slider = gui->addSlider(Speed1.getName(),Speed1.getMin(),Speed1.getMax(),Speed1);
speed2Slider = gui->addSlider(Speed2.getName(),Speed2.getMin(),Speed2.getMax(),Speed2);
//ofAddListener(gui->newGUIEvent, this, &ksdraw12129::guiEvent);
ofBaseDraws *pDrawSrc = ksResource::getResource();
if(!F.isAllocated())
F.allocate(pDrawSrc->getWidth(), pDrawSrc->getHeight(), GL_RGBA);
}
WidgetMain::WidgetMain(QWidget *parent)
: QWidget(parent)
, offset_()
, boardIndex_("")
, pUploadSetting_(NULL)
, pEditScene_(NULL)
, pFunctionArea_(NULL)
, pSerialSetting_(NULL)
, affirmType_(-1)
, pDustbin_(NULL)
, bDustbinShow_(false)
, type_(-1)
, pageIndex_(0)
, pAllBlockMenu_(NULL)
, pListWidget_(NULL)
, pSerialPortTool_(NULL)
{
setupUi(this);
initSetting();
initData();
initGui();
}
static int smi_bwc_config( MTK_SMI_BWC_CONFIG* p_conf , unsigned long * pu4LocalCnt)
{
int i;
unsigned long u4Concurrency = 0;
MTK_SMI_BWC_SCEN eFinalScen;
static MTK_SMI_BWC_SCEN ePreviousFinalScen = SMI_BWC_SCEN_CNT;
if((SMI_BWC_SCEN_CNT <= p_conf->scenario) || (0 > p_conf->scenario))
{
SMIERR("Incorrect SMI BWC config : 0x%x, how could this be...\n" , p_conf->scenario);
return -1;
}
//Debug - S
//SMIMSG("SMI setTo%d,%s,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , ePreviousFinalScen);
//Debug - E
spin_lock(&g_SMIInfo.SMI_lock);
if(p_conf->b_on_off)
{
//turn on certain scenario
g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] += 1;
if(NULL != pu4LocalCnt)
{
pu4LocalCnt[p_conf->scenario] += 1;
}
}
else
{
//turn off certain scenario
if(0 == g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario])
{
SMIMSG("Too many turning off for global SMI profile:%d,%d\n" , p_conf->scenario , g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario]);
}
else
{
g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] -= 1;
}
if(NULL != pu4LocalCnt)
{
if(0 == pu4LocalCnt[p_conf->scenario])
{
SMIMSG("Process : %s did too many turning off for local SMI profile:%d,%d\n" , current->comm ,p_conf->scenario , pu4LocalCnt[p_conf->scenario]);
}
else
{
pu4LocalCnt[p_conf->scenario] -= 1;
}
}
}
for(i=0 ; i < SMI_BWC_SCEN_CNT ; i++)
{
if(g_SMIInfo.pu4ConcurrencyTable[i])
{
u4Concurrency |= (1 << i);
}
}
if((1 << SMI_BWC_SCEN_VR) & u4Concurrency)
{
eFinalScen = SMI_BWC_SCEN_VR;
}
else if((1 << SMI_BWC_SCEN_VP) & u4Concurrency)
{
eFinalScen = SMI_BWC_SCEN_VP;
}
else
{
eFinalScen = SMI_BWC_SCEN_NORMAL;
}
if(ePreviousFinalScen == eFinalScen)
{
SMIMSG("Scen equal%d,don't change\n" , eFinalScen);
spin_unlock(&g_SMIInfo.SMI_lock);
return 0;
}
else
{
ePreviousFinalScen = eFinalScen;
}
/*turn on larb clock*/
for( i=0 ; i < SMI_LARB_NR ; i++){
larb_clock_on(i);
}
/*Bandwidth Limiter*/
switch( eFinalScen )
{
case SMI_BWC_SCEN_VP:
SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VP");
#if 1
M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read
M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel
M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs
M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0x961);//353/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x885A25);//549/4096 maximum grant counts, hard limiter, 2 read 2 write outstanding limit
M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL
M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA
M4U_WriteReg32(LARB0_BASE , 0x208 , 0x3);//WDMA
M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ
M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA
M4U_WriteReg32(LARB0_BASE , 0x214 , 0x1);//MDP_WDMA
M4U_WriteReg32(LARB0_BASE , 0x218 , 0x4);//MDP_ROTO
M4U_WriteReg32(LARB0_BASE , 0x21C , 0x2);//MDP_ROTCO
M4U_WriteReg32(LARB0_BASE , 0x220 , 0x2);//MDP_ROTVO
M4U_WriteReg32(LARB1_BASE , 0x200 , 0x6);//MC
M4U_WriteReg32(LARB1_BASE , 0x204 , 0x2);//PP
M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV
M4U_WriteReg32(LARB1_BASE , 0x20C , 0x3);//RD
M4U_WriteReg32(LARB1_BASE , 0x210 , 0x3);//WR
M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD
M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP
M4U_WriteReg32(LARB2_BASE , 0x200 , 0x1);//IMGO
M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O
M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI
M4U_WriteReg32(LARB2_BASE , 0x20C , 0x1);//IMGI
M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO
M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO
M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA
M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x220 , 0x2);//VENC_RD_COMV
M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV
M4U_WriteReg32(LARB2_BASE , 0x228 , 0x4);//VENC_RCPU
M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM
M4U_WriteReg32(LARB2_BASE , 0x230 , 0x2);//VENC_REF_LUMA
M4U_WriteReg32(LARB2_BASE , 0x234 , 0x1);//VENC_REF_CHROMA
M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x23C , 0x1);//VENC_CUR_LUMA
M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA
#endif
break;
case SMI_BWC_SCEN_VR:
SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VR");
#if 1
M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read
M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel
M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs
M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0xD4F);//1359/4096 maximum grant counts, soft limiter
M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x884912);// 274/4096 maximum grant counts, soft limiter, 2 read 2 write outstanding limit
M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL
M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA
M4U_WriteReg32(LARB0_BASE , 0x208 , 0x1);//WDMA
M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ
M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA
M4U_WriteReg32(LARB0_BASE , 0x214 , 0x2);//MDP_WDMA
M4U_WriteReg32(LARB0_BASE , 0x218 , 0x2);//MDP_ROTO
M4U_WriteReg32(LARB0_BASE , 0x21C , 0x4);//MDP_ROTCO
M4U_WriteReg32(LARB0_BASE , 0x220 , 0x1);//MDP_ROTVO
M4U_WriteReg32(LARB1_BASE , 0x200 , 0x1);//MC
M4U_WriteReg32(LARB1_BASE , 0x204 , 0x1);//PP
M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV
M4U_WriteReg32(LARB1_BASE , 0x20C , 0x1);//RD
M4U_WriteReg32(LARB1_BASE , 0x210 , 0x1);//WR
M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD
M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP
M4U_WriteReg32(LARB2_BASE , 0x200 , 0x6);//IMGO
M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O
M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI
M4U_WriteReg32(LARB2_BASE , 0x20C , 0x4);//IMGI
M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO
M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO
M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA
M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x220 , 0x1);//VENC_RD_COMV
M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV
M4U_WriteReg32(LARB2_BASE , 0x228 , 0x1);//VENC_RCPU
M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM
M4U_WriteReg32(LARB2_BASE , 0x230 , 0x4);//VENC_REF_LUMA
M4U_WriteReg32(LARB2_BASE , 0x234 , 0x2);//VENC_REF_CHROMA
M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA
M4U_WriteReg32(LARB2_BASE , 0x23C , 0x2);//VENC_CUR_LUMA
M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA
#endif
break;
case SMI_BWC_SCEN_NORMAL:
SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_SCEN_NORMAL");
initSetting();
default:
break;
}
/*turn off larb clock*/
for(i = 0 ; i < SMI_LARB_NR ; i++){
larb_clock_off(i);
}
spin_unlock(&g_SMIInfo.SMI_lock);
SMIMSG("ScenTo:%d,turn %s,Curr Scen:%d,%d,%d,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , eFinalScen ,
g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VR] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VP]);
//Debug usage - S
//smi_dumpDebugMsg();
//SMIMSG("Config:%d,%d,%d\n" , eFinalScen , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , (NULL == pu4LocalCnt ? (-1) : pu4LocalCnt[p_conf->scenario]));
//Debug usage - E
return 0;
}
int larb_reg_restore(int larb)
{
unsigned int regval,regval1,regval2;
unsigned int larb_base = gLarbBaseAddr[larb];
/*
unsigned int* pReg = pLarbRegBackUp[larb];
int i;
//warning: larb_con is controlled by set/clr
regval = *(pReg++);
M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval));
M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval));
M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) );
M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) );
for(i=0; i<3; i++)
{
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++));
M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++));
}
*/
//Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns
//Got to enable OSTD before engine starts
regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT);
regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0);
regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1);
if(0 == regval)
{
int retry_count = 0;
SMIMSG("Init OSTD for larb_base: 0x%x\n" , larb_base);
// Write 0x60 = 0xFFFF_FFFF, enable BW limiter
M4U_WriteReg32(larb_base , 0x60 , 0xffffffff);
// Polling 0x600 = 0xaaaa
for(retry_count= 0; retry_count<64; retry_count++)
{
if(M4U_ReadReg32(larb_base , 0x600) == 0xaaaa)
{
//Step3. Once it is found 0x600 == 0xaaaa, we can start to enable outstanding limiter and set outstanding limit
break;
}
SMIMSG("Larb: 0x%x busy : waiting for idle\n" , larb_base);
udelay(500);
}
// Write 0x60 = 0x0, disable BW limiter
M4U_WriteReg32(larb_base , 0x60 , 0x0);
// enable ISTD
M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff);
}
else
{
SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2);
smi_dumpDebugMsg();
SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2);
}
if(0 == g_bInited)
{
initSetting();
g_bInited = 1;
SMIMSG("SMI init\n");
}
// Show SMI always on register when larb 0 is enable
if(larb == 0){
SMIMSG("===SMI always on reg dump===\n");
SMIMSG("[0x5C0,0x5C4,0x5C8]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C0),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C4),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C8));
SMIMSG("[0x5CC,0x5D0]=[0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5CC),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5D0));
}
return 0;
}
