int main(void)
{
uint8_t TWIS_ResponseType;
init_modi();
init_io_ports();
init_timer();
set_outputs();
/*
** Start TWI Slave with address 15 and bitrate of 100000 Hz
*/
TWIS_Init();
/*
mainloop - Kommunikation mit dem master
*/
while (1)
{
if (TWIS_ResponseRequired(&TWIS_ResponseType))
{
switch (TWIS_ResponseType)
{
/*
** Slave is requested to read bytes from the master.
*/
case TW_SR_SLA_ACK:
{
outputdata.ports = TWIS_ReadAck();
outputdata.ports += TWIS_ReadAck() << 8;
uint8_t i;
for (i = 0; i < PWM_CHAN - 1; i++)
outputdata.pwmval[i] = TWIS_ReadAck();
outputdata.pwmval[i] = TWIS_ReadNack();
TWIS_Stop(); // I2C stop
set_outputs();
}
break;
/*
** Slave is requested to send bytes from the master.
*/
case TW_ST_SLA_ACK:
TWIS_Write(outputdata.ports);
TWIS_Write(outputdata.ports >> 8);
for (int read_p = 0; read_p < PWM_CHAN; read_p++)
TWIS_Write(outputdata.pwmval[read_p]);
TWIS_Stop();
break;
default:
TWIS_Stop();
break;
}
}
wdt_reset();
}
}
/* ****************************************************************************/
int main() {
SYSTEMConfigPerformance(FCY); // setup system to improve performance
init_io_ports(); // initialize I/O ports
LCD_Setup(); // setup the LCD
// dis_RES=1;
// dis_CS=1;
// dis_D_C=1;
// dis_E_RD=1;
// dis_R_W=1;
// dis_EN=1;
// LATE=0xFF;
while(1){ // main loop
delay_clock(10000);
LATDbits.LATD8=1;
delay_clock(10000);
LATDbits.LATD8=0;
}
}
int main(void)
{
int i, spi_timeout;
unsigned long counter;
/* Disable JTAG port so we get our I/O pins back */
DDPCONbits.JTAGEN = 0;
/* Enable optimal performance */
SYSTEMConfigPerformance(GetSystemClock());
/* Use 1:1 CPU Core:Peripheral clocks */
OSCSetPBDIV(OSC_PB_DIV_1);
/* configure the core timer roll-over rate */
OpenCoreTimer(CORE_TICK_RATE);
/* set up the core timer interrupt */
mConfigIntCoreTimer((CT_INT_ON | CT_INT_PRIOR_6 | CT_INT_SUB_PRIOR_0));
/* enable multi vector interrupts */
INTConfigureSystem(INT_SYSTEM_CONFIG_MULT_VECTOR);
INTEnableInterrupts();
map_peripherals();
init_io_ports();
configure_pwm();
init_spi();
init_dma();
/* wait until tx buffer is filled up */
while (!SPI2STATbits.SPITBF);
reset_board();
spi_data_ready = 0;
spi_timeout = 0;
counter = 0;
/* enable watchdog */
WDTCONSET = 0x8000;
/* main loop */
while (1) {
if (spi_data_ready) {
spi_data_ready = 0;
/* the first element received is a command string */
switch (rxBuf[0]) {
case 0x5453523E: /* >RST */
reset_board();
break;
case 0x314D433E: /* >CM1 */
stepgen_update_input((const void *)&rxBuf[1]);
stepgen_get_position((void *)&txBuf[1]);
break;
case 0x324D433E: /* >CM2 */
update_outputs(rxBuf[1]);
update_pwm_duty((uint32_t *)&rxBuf[2]);
txBuf[1] = read_inputs();
break;
case 0x4746433E: /* >CFG */
stepgen_update_stepwidth(rxBuf[1]);
update_pwm_period(rxBuf[2]);
stepgen_reset();
break;
case 0x5453543E: /* >TST */
for (i=0; i<BUFSIZE; i++)
txBuf[i] = rxBuf[i] ^ ~0;
break;
}
}
/* if rx buffer is half-full, update the integrity check.
There isn't enough time if we wait for complete transfer */
if (DCH0INTbits.CHDHIF) {
DCH0INTCLR = 1<<4; /* clear flag */
txBuf[0] = rxBuf[0] ^ ~0;
}
/* if rx buffer is full, data from spi bus is ready */
if (DCH0INTbits.CHBCIF) {
DCH0INTCLR = 1<<3; /* clear flag */
spi_data_ready = 1;
spi_timeout = SPI_TIMEOUT;
}
/* reset the board if there is no SPI activity */
if (spi_timeout)
spi_timeout--;
if (spi_timeout == 1) {
DCH0ECONSET=BIT_6; /* abort DMA transfers */
DCH1ECONSET=BIT_6;
init_spi();
init_dma();
reset_board();
/* wait until tx buffer is filled up */
while (!SPI2STATbits.SPITBF);
}
/* blink onboard led */
if (!(counter++ % (spi_timeout ? 0x10000 : 0x40000))) {
LED_TOGGLE;
}
/* keep alive */
WDTCONSET = 0x01;
}
return 0;
}
