/* init_rings */
int init_rings(ll_socket_t *ll_socket)
{
// 1) initialize rx ring
if ( ( ll_socket->rx_ring_len
= init_ring( ll_socket->rx_socket_fd, PACKET_RX_RING,
FRAMES_PER_BLOCK, NO_BLOCKS,
&ll_socket->rx_ring_buffer ) )
< 0 )
{
log_app_msg("Could not set initialize RX ring.");
return(EX_ERR);
}
// 2) initialize tx ring
if ( ( ll_socket->tx_ring_len
= init_ring( ll_socket->tx_socket_fd, PACKET_TX_RING,
FRAMES_PER_BLOCK, NO_BLOCKS,
&ll_socket->tx_ring_buffer ) )
< 0 )
{
log_app_msg("Could not set initialize TX ring.");
return(EX_ERR);
}
// 3) set destination address for both kernel rings
if ( set_sockaddr_ll(ll_socket,0) < 0 ) //puxen 0 por poñer algo
{
log_app_msg("Could not set sockaddr_ll for TX/RX rings.");
return(EX_ERR);
}
return(EX_OK);
}
static void
mi_mic_dma_chan_setup(struct dma_channel *ch, struct mic_dma_ctx_t *dma_ctx)
{
ch->next_write_index = ch->chan->cached_tail;
init_ring(&ch->poll_ring, MAX_POLLING_BUFFERS, dma_ctx->device_num);
ch->intr_ring.comp_cb_array =
kzalloc(sizeof(*ch->intr_ring.comp_cb_array) * NUM_COMP_BUFS, GFP_KERNEL);
init_ring(&ch->intr_ring.ring, NUM_COMP_BUFS, dma_ctx->device_num);
ch->intr_ring.old_tail = 0;
}
static void w89c840_reset(struct nic *nic)
{
int i;
writel(0x00000001, ioaddr + PCIBusCfg);
init_ring();
writel(virt_to_bus(w840private.rx_ring), ioaddr + RxRingPtr);
writel(virt_to_bus(w840private.tx_ring), ioaddr + TxRingPtr);
for (i = 0; i < ETH_ALEN; i++)
writeb(nic->node_addr[i], ioaddr + StationAddr + i);
writel(0xE010, ioaddr + PCIBusCfg);
writel(0, ioaddr + RxStartDemand);
w840private.csr6 = 0x20022002;
check_duplex();
set_rx_mode();
writel(0x1A0F5, ioaddr + IntrStatus);
writel(0x1A0F5, ioaddr + IntrEnable);
#if defined(W89C840_DEBUG)
printf("winbond-840 : Done reset.\n");
#endif
}
int
main(int argc, char **argv)
{ dtd_dialect dialect = DL_SGML;
init_ring();
program = argv[0];
argv++;
argc--;
while(argc > 0 && argv[0][0] == '-')
{ if ( streq(argv[0], "-xml") )
{ dialect = DL_XML;
argc--;
argv++;
} else if ( streq(argv[0], "-sgml") )
{ dialect = DL_SGML;
argc--;
argv++;
} else
{ usage();
exit(1);
}
}
if ( argc == 1 )
{ int wl = mbstowcs(NULL, argv[0], 0);
if ( wl > 0 )
{ wchar_t *ws = malloc((wl+1)*sizeof(wchar_t));
dtd *dtd;
mbstowcs(ws, argv[0], wl+1);
dtd = file_to_dtd(ws, L"test", dialect);
if ( dtd )
{ prolog_print_dtd(dtd, PL_PRINT_ALL & ~PL_PRINT_PENTITIES);
return 0;
}
} else
{ perror("mbstowcs");
exit(1);
}
}
usage();
return 1;
}
int initialise_buffers(int buflines)
{
bufs=malloc(sizeof(buffer));
if(!bufs)
return(1);
init_buffer(0, STATUS, "status", buflines); // buf 0 is always STATUS
nbufs=1;
cbuf=0;
bufs[0].live=true; // STATUS is never dead
bufs[0].nick=nick;
nick=NULL;
bufs[0].ilist=igns;
add_to_buffer(0, STA, QUIET, 0, false, GPL_TAIL, "quirc -- ");
init_ring(&d_buf);
d_buf.loop=true;
return(0);
}
/**************************************************************************
w89c840_reset - Reset adapter
***************************************************************************/
static void w89c840_reset(struct nic *nic)
{
int i;
/* Reset the chip to erase previous misconfiguration.
No hold time required! */
writel(0x00000001, ioaddr + PCIBusCfg);
init_ring();
writel(virt_to_bus(w840private.rx_ring), ioaddr + RxRingPtr);
writel(virt_to_bus(w840private.tx_ring), ioaddr + TxRingPtr);
for (i = 0; i < ETH_ALEN; i++)
writeb(nic->node_addr[i], ioaddr + StationAddr + i);
/* Initialize other registers. */
/* Configure the PCI bus bursts and FIFO thresholds.
486: Set 8 longword cache alignment, 8 longword burst.
586: Set 16 longword cache alignment, no burst limit.
Cache alignment bits 15:14 Burst length 13:8
0000 <not allowed> 0000 align to cache 0800 8 longwords
4000 8 longwords 0100 1 longword 1000 16 longwords
8000 16 longwords 0200 2 longwords 2000 32 longwords
C000 32 longwords 0400 4 longwords
Wait the specified 50 PCI cycles after a reset by initializing
Tx and Rx queues and the address filter list. */
writel(0xE010, ioaddr + PCIBusCfg);
writel(0, ioaddr + RxStartDemand);
w840private.csr6 = 0x20022002;
check_duplex();
set_rx_mode();
/* Do not enable the interrupts Etherboot doesn't need them */
/*
writel(0x1A0F5, ioaddr + IntrStatus);
writel(0x1A0F5, ioaddr + IntrEnable);
*/
#if defined(W89C840_DEBUG)
printf("winbond-840 : Done reset.\n");
#endif
}
int add_to_ring(ring *r, mtype lm, const char *lt, const char *ltag)
{
if(!r->nlines) init_ring(r);
int p=r->ptr;
if(!(++r->ptr<r->nlines))
{
if(r->loop)
{
r->filled=true;
r->ptr-=r->nlines;
}
else
{
r->ptr=p;
r->errs++;
return(1);
}
}
r->lt[p]=strdup(lt);
r->ltag[p]=strdup(ltag);
r->lm[p]=lm;
r->ts[p]=time(NULL);
return(0);
}
void Renderer::init()
{
init_shaders();
ortho = new Matrix4f();
mx_translate = new Matrix4f();
mx_scale = new Matrix4f();
mx_rotate = new Matrix4f();
init_rect();
init_grid();
InitPassGrid();
init_line();
init_tower();
init_circle();
init_ring();
InitTriangle();
InitPolygon();
initHexGrid();
glEnable(GL_BLEND);
glBlendFunc(GL_SRC_ALPHA,GL_ONE_MINUS_SRC_ALPHA);
glCullFace(GL_BACK);
}
static int netdev_open(struct net_device *dev)
{
struct netdev_private *np = dev->priv;
long ioaddr = dev->base_addr;
int i;
/* Do we need to reset the chip??? */
i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
if (i)
return i;
if (debug > 1)
printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
dev->name, dev->irq);
init_ring(dev);
writel(np->rx_ring_dma, ioaddr + RxListPtr);
/* The Tx list pointer is written as packets are queued. */
for (i = 0; i < 6; i++)
writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
/* Initialize other registers. */
/* Configure the PCI bus bursts and FIFO thresholds. */
if (dev->if_port == 0)
dev->if_port = np->default_port;
np->mcastlock = (spinlock_t) SPIN_LOCK_UNLOCKED;
set_rx_mode(dev);
writew(0, ioaddr + IntrEnable);
writew(0, ioaddr + DownCounter);
/* Set the chip to poll every N*320nsec. */
writeb(100, ioaddr + RxDescPoll);
writeb(127, ioaddr + TxDescPoll);
netif_start_queue(dev);
/* Enable interrupts by setting the interrupt mask. */
writew(IntrRxDone | IntrRxDMADone | IntrPCIErr | IntrDrvRqst | IntrTxDone
| StatsMax | LinkChange, ioaddr + IntrEnable);
writew(StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
if (debug > 2)
printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
"MAC Control %x, %4.4x %4.4x.\n",
dev->name, readl(ioaddr + RxStatus), readb(ioaddr + TxStatus),
readl(ioaddr + MACCtrl0),
readw(ioaddr + MACCtrl1), readw(ioaddr + MACCtrl0));
/* Set the timer to check for link beat. */
init_timer(&np->timer);
np->timer.expires = jiffies + 3*HZ;
np->timer.data = (unsigned long)dev;
np->timer.function = &netdev_timer; /* timer handler */
add_timer(&np->timer);
return 0;
}
int init_buffer(int buf, btype type, const char *bname, int nlines)
{
bufs[buf].type=type;
bufs[buf].bname=strdup(bname);
if(type==SERVER)
bufs[buf].serverloc=strdup(bname);
else
bufs[buf].serverloc=NULL;
bufs[buf].realsname=NULL;
bufs[buf].nlist=NULL;
bufs[buf].us=NULL;
bufs[buf].ilist=NULL;
bufs[buf].handle=0;
bufs[buf].server=0;
bufs[buf].nick=NULL;
bufs[buf].topic=NULL;
bufs[buf].logf=NULL;
bufs[buf].nlines=nlines;
bufs[buf].ptr=0;
bufs[buf].scroll=0;
bufs[buf].ascroll=0;
bufs[buf].lm=malloc(nlines*sizeof(mtype));
bufs[buf].lq=malloc(nlines*sizeof(prio));
bufs[buf].lp=malloc(nlines);
bufs[buf].ls=malloc(nlines*sizeof(bool));
bufs[buf].lt=malloc(nlines*sizeof(char *));
int i;
for(i=0;i<bufs[buf].nlines;i++)
{
bufs[buf].lt[i]=NULL;
}
bufs[buf].ltag=malloc(nlines*sizeof(char *));
for(i=0;i<bufs[buf].nlines;i++)
{
bufs[buf].ltag[i]=NULL;
}
bufs[buf].lpl=malloc(nlines*sizeof(int));
bufs[buf].lpc=malloc(nlines*sizeof(colour));
bufs[buf].lpt=malloc(nlines*sizeof(char **));
for(i=0;i<nlines;i++)
{
bufs[buf].lpl[i]=0;
bufs[buf].lpc[i]=(colour){.fore=7, .back=0, .hi=false, .ul=false};
bufs[buf].lpt[i]=NULL;
}
bufs[buf].dirty=false;
bufs[buf].ts=malloc(nlines*sizeof(time_t));
bufs[buf].filled=false;
bufs[buf].alert=false;
bufs[buf].hi_alert=0;
bufs[buf].ping=0;
bufs[buf].last=time(NULL);
bufs[buf].namreply=false;
bufs[buf].live=false;
bufs[buf].conninpr=false;
initibuf(&bufs[buf].input);
bufs[buf].casemapping=RFC1459;
if(type==SERVER)
{
bufs[buf].npfx=2;
bufs[buf].prefixes=malloc(2*sizeof(prefix));
bufs[buf].prefixes[0]=(prefix){.letter='o', .pfx='@'};
bufs[buf].prefixes[1]=(prefix){.letter='v', .pfx='+'};
}
else
{
bufs[buf].npfx=0;
bufs[buf].prefixes=NULL;
}
bufs[buf].autoent=NULL;
bufs[buf].conf=conf;
bufs[buf].key=NULL;
bufs[buf].lastkey=NULL;
return(0);
}
int free_buffer(int buf)
{
if(bufs[buf].live)
{
add_to_buffer(buf, ERR, NORMAL, 0, false, "Buffer is still live!", "free_buffer:");
return(1);
}
else
{
free(bufs[buf].bname);
free(bufs[buf].serverloc);
free(bufs[buf].realsname);
n_free(bufs[buf].nlist);
bufs[buf].nlist=NULL;
n_free(bufs[buf].ilist);
bufs[buf].ilist=NULL;
free(bufs[buf].nick);
free(bufs[buf].topic);
if(bufs[buf].logf)
fclose(bufs[buf].logf);
free(bufs[buf].lm);
free(bufs[buf].lq);
free(bufs[buf].lp);
free(bufs[buf].ls);
int l;
if(bufs[buf].lt)
{
for(l=0;l<bufs[buf].nlines;l++)
free(bufs[buf].lt[l]);
free(bufs[buf].lt);
}
if(bufs[buf].ltag)
{
for(l=0;l<bufs[buf].nlines;l++)
free(bufs[buf].ltag[l]);
free(bufs[buf].ltag);
}
if(bufs[buf].lpt)
{
for(l=0;l<bufs[buf].nlines;l++)
{
if(bufs[buf].lpt[l])
{
if(bufs[buf].lpl)
{
int p;
for(p=0;p<bufs[buf].lpl[l];p++)
{
free(bufs[buf].lpt[l][p]);
}
}
free(bufs[buf].lpt[l]);
}
}
free(bufs[buf].lpt);
}
free(bufs[buf].lpl);
free(bufs[buf].lpc);
free(bufs[buf].ts);
freeibuf(&bufs[buf].input);
free(bufs[buf].prefixes);
free(bufs[buf].key);
free(bufs[buf].lastkey);
if(cbuf>=buf)
cbuf--;
nbufs--;
int b;
for(b=buf;b<nbufs;b++)
{
bufs[b]=bufs[b+1];
}
for(b=0;b<nbufs;b++)
{
if(bufs[b].server==buf)
{
bufs[b].server=0; // orphaned; should not happen
bufs[b].live=false;
bufs[b].handle=0; // just in case
}
else if(bufs[b].server>buf)
{
bufs[b].server--;
}
}
if(nbufs) redraw_buffer();
return(0);
}
}
int add_to_buffer(int buf, mtype lm, prio lq, char lp, bool ls, const char *lt, const char *ltag)
{
if(buf>=nbufs)
{
if(bufs&&buf)
{
add_to_buffer(0, ERR, NORMAL, 0, false, "Line was written to bad buffer! Contents below.", "add_to_buffer(): ");
add_to_buffer(0, lm, NORMAL, lp, ls, lt, ltag);
}
return(1);
}
if(!debug&&(lq==DEBUG))
{
if(!d_buf.nlines)
{
init_ring(&d_buf);
d_buf.loop=true;
}
return(add_to_ring(&d_buf, lm, lt, ltag));
}
int optr=bufs[buf].ptr;
bool scrollisptr=(bufs[buf].scroll==bufs[buf].ptr)&&(bufs[buf].ascroll==0);
bufs[buf].lm[bufs[buf].ptr]=lm;
bufs[buf].lq[bufs[buf].ptr]=lq;
bufs[buf].lp[bufs[buf].ptr]=lp;
bufs[buf].ls[bufs[buf].ptr]=ls;
free(bufs[buf].lt[bufs[buf].ptr]);
bufs[buf].lt[bufs[buf].ptr]=strdup(lt);
free(bufs[buf].ltag[bufs[buf].ptr]);
bufs[buf].ltag[bufs[buf].ptr]=strdup(ltag);
time_t ts=bufs[buf].ts[bufs[buf].ptr]=time(NULL);
bufs[buf].ptr=(bufs[buf].ptr+1)%bufs[buf].nlines;
if(scrollisptr)
{
bufs[buf].scroll=bufs[buf].ptr;
bufs[buf].ascroll=0;
}
if(bufs[buf].ptr==0)
bufs[buf].filled=true;
render_line(buf, optr);
if(buf==cbuf)
{
int e=redraw_buffer();
if(e) return(e);
}
else
{
if(!(
(bufs[buf].conf&&((lm==JOIN)||(lm==PART)||(lm==NICK)||(lm==MODE)||(lm==QUIT)))
||
(quiet&&(lq==QUIET))
||
(!debug&&(lq==DEBUG))
))
bufs[buf].alert=true;
}
if(bufs[buf].logf)
{
int e=log_add(bufs[buf].logf, bufs[buf].logt, lm, lq, lp, ls, lt, ltag, ts);
if(e) return(e);
}
return(0);
}
int redraw_buffer(void)
{
if(bufs[cbuf].dirty)
{
int e=render_buffer(cbuf);
if(e) return(e);
if(bufs[cbuf].dirty) return(1);
}
int uline=bufs[cbuf].scroll;
int pline=bufs[cbuf].ascroll;
while(pline<0)
{
uline--;
if((bufs[cbuf].filled)&&(uline==bufs[cbuf].ptr))
{
uline++;
pline=0;
break;
}
if(uline<0)
{
if(bufs[cbuf].filled)
uline+=bufs[cbuf].nlines;
else
{
uline=0;
pline=0;
break;
}
}
pline+=bufs[cbuf].lpl[uline];
}
if(uline==bufs[cbuf].ptr)
{
pline=0;
}
while(pline>=bufs[cbuf].lpl[uline])
{
pline-=bufs[cbuf].lpl[uline];
if(bufs[cbuf].filled)
{
if(uline==bufs[cbuf].ptr)
{
pline=0;
break;
}
uline=(uline+1)%bufs[cbuf].nlines;
}
else
{
if(uline>=bufs[cbuf].ptr)
{
uline=bufs[cbuf].ptr;
pline=0;
break;
}
uline++;
}
}
bufs[cbuf].scroll=uline;
bufs[cbuf].ascroll=pline;
int row=height-2;
//setcolour(bufs[cbuf].lpc[uline]);
while(row>(tsb?1:0))
{
bool breakit=false;
pline--;
while(pline<0)
{
uline--;
if(uline<0)
{
if(bufs[cbuf].filled)
uline+=bufs[cbuf].nlines;
else
{
breakit=true;
pline=0;
break;
}
}
if(uline==bufs[cbuf].ptr)
{
breakit=true;
break;
}
pline+=bufs[cbuf].lpl[uline];
}
if(breakit) break;
locate(row, 0);
fputs(bufs[cbuf].lpt[uline][pline], stdout);
if(!full_width_colour) resetcol();
clr();
row--;
}
resetcol();
while(row>(tsb?1:0))
{
locate(row--, 0);
clr();
}
switch(bufs[cbuf].type)
{
case STATUS:
settitle("quIRC - status");
break;
case SERVER: // have to scope it for the cstr 'variably modified type'
{
char cstr[16+strlen(bufs[cbuf].bname)];
sprintf(cstr, "quIRC - %s", bufs[cbuf].bname);
settitle(cstr);
}
break;
case CHANNEL: // have to scope it for the cstr 'variably modified type'
{
char cstr[16+strlen(bufs[cbuf].bname)+strlen(SERVER(cbuf).bname)];
sprintf(cstr, "quIRC - %s on %s", bufs[cbuf].bname, SERVER(cbuf).bname);
settitle(cstr);
}
break;
case PRIVATE: // have to scope it for the cstr 'variably modified type'
{
char cstr[16+strlen(bufs[cbuf].bname)+strlen(SERVER(cbuf).bname)];
sprintf(cstr, "quIRC - <%s> on %s", bufs[cbuf].bname, SERVER(cbuf).bname);
settitle(cstr);
}
break;
default:
settitle("quIRC");
break;
}
if(tsb)
titlebar();
bufs[cbuf].alert=false;
return(0);
}
int mark_buffer_dirty(int buf)
{
bufs[buf].dirty=true;
return(0);
}
static int netdev_open(struct device *dev)
{
struct netdev_private *np = (struct netdev_private *)dev->priv;
long ioaddr = dev->base_addr;
int i;
/* Reset the chip. */
writew(CmdReset, ioaddr + ChipCmd);
if (request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev))
return -EAGAIN;
if (debug > 1)
printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
dev->name, dev->irq);
MOD_INC_USE_COUNT;
init_ring(dev);
writel(virt_to_bus(np->rx_ring), ioaddr + RxRingPtr);
writel(virt_to_bus(np->tx_ring), ioaddr + TxRingPtr);
for (i = 0; i < 6; i++)
writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
/* Initialize other registers. */
writew(0x0006, ioaddr + PCIConfig); /* Tune configuration??? */
/* Configure the FIFO thresholds. */
writeb(0x20, ioaddr + TxConfig); /* Initial threshold 32 bytes */
np->tx_thresh = 0x20;
np->rx_thresh = 0x60; /* Written in set_rx_mode(). */
if (dev->if_port == 0)
dev->if_port = np->default_port;
dev->tbusy = 0;
dev->interrupt = 0;
np->in_interrupt = 0;
set_rx_mode(dev);
dev->start = 1;
/* Enable interrupts by setting the interrupt mask. */
writew(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow| IntrRxDropped|
IntrTxDone | IntrTxAbort | IntrTxUnderrun |
IntrPCIErr | IntrStatsMax | IntrLinkChange | IntrMIIChange,
ioaddr + IntrEnable);
np->chip_cmd = CmdStart|CmdTxOn|CmdRxOn|CmdNoTxPoll;
if (np->duplex_lock)
np->chip_cmd |= CmdFDuplex;
writew(np->chip_cmd, ioaddr + ChipCmd);
check_duplex(dev);
if (debug > 2)
printk(KERN_DEBUG "%s: Done netdev_open(), status %4.4x "
"MII status: %4.4x.\n",
dev->name, readw(ioaddr + ChipCmd),
mdio_read(dev, np->phys[0], 1));
/* Set the timer to check for link beat. */
init_timer(&np->timer);
np->timer.expires = RUN_AT(1);
np->timer.data = (unsigned long)dev;
np->timer.function = &netdev_timer; /* timer handler */
add_timer(&np->timer);
return 0;
}
