int main( int argc, char **argv ){
// Init the instructions
init_instr_memory();
// CLOCK CYCLE LOOP
int instr_buffer;
while( 1 ){
// NOTE: Order matters. All functions should fetch value
// from pipelined reg before the previous stage override the
// reg values
write_back();
memory_write();
execute_2();
execute_1();
instruction_decode();
instruction_fetch();
clk++;
}
free( instruction_memory );
free( data_memory );
exit( 0 );
}
void process_instruction(){
// update stage
write_back();
if( if_register.stall == 0 ) {
instruction_fetch();
} else {
if_register.stall += -1;
}
instruction_decode();
execute_instruction();
memory_access();
btb_move_right();
int index = (CURRENT_STATE.PC - MEM_TEXT_START - 4)/4 ;
// printf(" index %d, NUM_INST %d \n",index,NUM_INST);
if( index == NUM_INST ) {
CURRENT_STATE.PC += -4;
// printf("Run bit unset pc: %x\n",CURRENT_STATE.PC);
}
}
void Step(void)
{
/* fetch instruction from memory */
Halt = instruction_fetch(PC,Mem,&instruction);
if(!Halt)
{
/* partition the instruction */
instruction_partition(instruction,&op,&r1,&r2,&r3,&funct,&offset,&jsec);
/* instruction decode */
Halt = instruction_decode(op,&controls);
}
if(!Halt)
{
/* read_register */
read_register(r1,r2,Reg,&data1,&data2);
/* sign_extend */
sign_extend(offset,&extended_value);
/* ALU */
Halt = ALU_operations(data1,data2,extended_value,funct,controls.ALUOp,controls.ALUSrc,&ALUresult,&Zero);
}
if(!Halt)
{
/* read/write memory */
Halt = rw_memory(ALUresult,data2,controls.MemWrite,controls.MemRead,&memdata,Mem);
}
if(!Halt)
{
/* write to register */
write_register(r2,r3,memdata,ALUresult,controls.RegWrite,controls.RegDst,controls.MemtoReg,Reg);
/* PC update */
PC_update(jsec,extended_value,controls.Branch,controls.Jump,Zero,&PC);
}
}
int main(){
int i=0;
initialize();
//cycle0
if(test==1) printf(">>cycle %d\n",cycle);
instruction_fetch(1);
initial_SNAP();
//cycle1
if(test==1) printf(">>cycle %d\n",cycle);
instruction_decode(ID_index);
instruction_fetch(1);
append_SNAP();
//cycle2
if(test==1) printf(">>cycle %d\n",cycle);
execution(EX_index);
instruction_decode(ID_index);
instruction_fetch(1);
append_ERROR();
if(halt==1 || halt_count==5){
return 0;
}
append_SNAP();
if(stall){
memory(DM_index);
execution(0);
instruction_decode(0);
//instruction_fetch(0);
append_ERROR();
if(halt==1 || halt_count==5) return 0;
stall=0;
append_SNAP();
}
if(flush){
flush=0;
}
//cycle3
if(test==1) printf(">>cycle %d\n",cycle);
memory(DM_index);
execution(EX_index);
instruction_decode(ID_index);
instruction_fetch(1);
append_ERROR();
if(halt==1 || halt_count==5){
return 0;
}
append_SNAP();
if(stall){
write_back(WB_index);
memory(DM_index);
execution(0);
instruction_decode(0);
//instruction_fetch(0);
append_ERROR();
if(halt==1 || halt_count==5) return 0;
stall=0;
append_SNAP();
}
if(flush){
flush=0;
}
while(i<50){
i++;
if(test==1) printf(">>cycle %d\n",cycle);
write_back(WB_index);
memory(DM_index);
execution(EX_index);
instruction_decode(ID_index);
instruction_fetch(1);
append_ERROR();
if(halt==1 || halt_count==5){
break;
}
append_SNAP();
if(stall){
write_back(WB_index);
memory(DM_index);
execution(0);
instruction_decode(0);
//instruction_fetch(0);
append_ERROR();
if(halt==1 || halt_count==5) return 0;
stall=0;
append_SNAP();
}
if(flush){
flush=0;
}
}
return 0;
}
