static bool need_tile_offset_workaround(struct brw_context *brw, struct intel_renderbuffer *irb) { uint32_t tile_x, tile_y; if (brw->has_surface_tile_offset) return false; intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y); return tile_x != 0 || tile_y != 0; }
static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct gl_context *ctx = &intel->ctx; struct gl_framebuffer *fb = ctx->DrawBuffer; /* _NEW_BUFFERS */ struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL); struct intel_mipmap_tree *stencil_mt = NULL; struct intel_region *hiz_region = NULL; unsigned int len; bool separate_stencil = false; if (depth_irb && depth_irb->mt && depth_irb->mt->hiz_mt) { hiz_region = depth_irb->mt->hiz_mt->region; } /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both * non-pipelined state that will need the PIPE_CONTROL workaround. */ if (intel->gen == 6) { intel_emit_post_sync_nonzero_flush(intel); intel_emit_depth_stall_flushes(intel); } /* Find the real separate stencil mt if present. */ if (stencil_irb) { stencil_mt = stencil_irb->mt; if (stencil_mt->stencil_mt) stencil_mt = stencil_mt->stencil_mt; if (stencil_mt->format == MESA_FORMAT_S8) separate_stencil = true; } /* If there's a packed depth/stencil bound to stencil only, we need to * emit the packed depth/stencil buffer packet. */ if (!depth_irb && stencil_irb && !separate_stencil) depth_irb = stencil_irb; if (intel->gen >= 6) len = 7; else if (intel->is_g4x || intel->gen == 5) len = 6; else len = 5; if (!depth_irb && !separate_stencil) { BEGIN_BATCH(len); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); if (intel->is_g4x || intel->gen >= 5) OUT_BATCH(0); if (intel->gen >= 6) OUT_BATCH(0); ADVANCE_BATCH(); } else if (!depth_irb && separate_stencil) { /* * There exists a separate stencil buffer but no depth buffer. * * The stencil buffer inherits most of its fields from * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and * height. * * Since the stencil buffer has quirky pitch requirements, its region * was allocated with half height and double cpp. So we need * a multiplier of 2 to obtain the surface's real height. * * Enable the hiz bit because it and the separate stencil bit must have * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit * 1.21 "Separate Stencil Enable": * [DevIL]: If this field is enabled, Hierarchical Depth Buffer * Enable must also be enabled. * * [DevGT]: This field must be set to the same value (enabled or * disabled) as Hierarchical Depth Buffer Enable * * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1, * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface: * [DevGT+]: This field must be set to TRUE. */ struct intel_region *region = stencil_mt->region; assert(intel->has_separate_stencil); BEGIN_BATCH(len); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (1 << 21) | /* separate stencil enable */ (1 << 22) | /* hiz enable */ (BRW_TILEWALK_YMAJOR << 26) | (1 << 27) | /* tiled surface */ (BRW_SURFACE_2D << 29)); OUT_BATCH(0); OUT_BATCH(((region->width - 1) << 6) | (2 * region->height - 1) << 19); OUT_BATCH(0); OUT_BATCH(0); if (intel->gen >= 6) OUT_BATCH(0); ADVANCE_BATCH(); } else { struct intel_region *region = depth_irb->mt->region; uint32_t tile_x, tile_y, offset; /* If using separate stencil, hiz must be enabled. */ assert(!separate_stencil || hiz_region); offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y); assert(intel->gen < 6 || region->tiling == I915_TILING_Y); assert(!hiz_region || region->tiling == I915_TILING_Y); BEGIN_BATCH(len); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH(((region->pitch * region->cpp) - 1) | (brw_depthbuffer_format(brw) << 18) | ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */ ((hiz_region ? 1 : 0) << 22) | /* hiz enable */ (BRW_TILEWALK_YMAJOR << 26) | ((region->tiling != I915_TILING_NONE) << 27) | (BRW_SURFACE_2D << 29)); OUT_RELOC(region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, offset); OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) | ((region->width - 1) << 6) | ((region->height - 1) << 19)); OUT_BATCH(0); if (intel->is_g4x || intel->gen >= 5) OUT_BATCH(tile_x | (tile_y << 16)); else assert(tile_x == 0 && tile_y == 0); if (intel->gen >= 6) OUT_BATCH(0); ADVANCE_BATCH(); } if (hiz_region || separate_stencil) { /* * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate * stencil enable' and 'hiz enable' bits were set. Therefore we must * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted; * failure to do so causes hangs on gen5 and a stall on gen6. */ /* Emit hiz buffer. */ if (hiz_region) { BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); OUT_RELOC(hiz_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); ADVANCE_BATCH(); } else { BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* Emit stencil buffer. */ if (separate_stencil) { struct intel_region *region = stencil_mt->region; BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); OUT_BATCH(region->pitch * region->cpp - 1); OUT_RELOC(region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); ADVANCE_BATCH(); } else { BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } } /* * On Gen >= 6, emit clear params for safety. If using hiz, then clear * params must be emitted. * * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS: * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet * when HiZ is enabled and the DEPTH_BUFFER_STATE changes. */ if (intel->gen >= 6 || hiz_region) { if (intel->gen == 6) intel_emit_post_sync_nonzero_flush(intel); BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2)); OUT_BATCH(0); ADVANCE_BATCH(); } }
static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct gl_context *ctx = &intel->ctx; struct gl_framebuffer *fb = ctx->DrawBuffer; /* _NEW_BUFFERS */ struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH); struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL); /* Gen7 doesn't support packed depth/stencil */ assert(srb == NULL || srb != drb); if (drb == NULL) { uint32_t dw1 = BRW_DEPTHFORMAT_D32_FLOAT << 18; uint32_t dw3 = 0; if (srb == NULL) { dw1 |= (BRW_SURFACE_NULL << 29); } else { struct intel_region *region = srb->region; /* _NEW_STENCIL: enable stencil buffer writes */ dw1 |= ((ctx->Stencil.WriteMask != 0) << 27); /* 3DSTATE_STENCIL_BUFFER inherits surface type and dimensions. */ dw1 |= (BRW_SURFACE_2D << 29); dw3 = ((region->width - 1) << 4) | ((2 * region->height - 1) << 18); } BEGIN_BATCH(7); OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); OUT_BATCH(dw1); OUT_BATCH(0); OUT_BATCH(dw3); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } else { struct intel_region *region = drb->region; uint32_t tile_x, tile_y, offset; offset = intel_renderbuffer_tile_offsets(drb, &tile_x, &tile_y); assert(region->tiling == I915_TILING_Y); /* _NEW_DEPTH, _NEW_STENCIL */ BEGIN_BATCH(7); OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); OUT_BATCH(((region->pitch * region->cpp) - 1) | (gen7_depth_format(brw) << 18) | (0 << 22) /* no HiZ buffer */ | ((srb != NULL && ctx->Stencil.WriteMask != 0) << 27) | ((ctx->Depth.Mask != 0) << 28) | (BRW_SURFACE_2D << 29)); OUT_RELOC(region->buffer, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, offset); OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18)); OUT_BATCH(0); OUT_BATCH(tile_x | (tile_y << 16)); OUT_BATCH(0); ADVANCE_BATCH(); } BEGIN_BATCH(4); OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); if (srb == NULL) { BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } else { BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); OUT_BATCH(srb->region->pitch * srb->region->cpp - 1); OUT_RELOC(srb->region->buffer, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); ADVANCE_BATCH(); } BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); }
/** * \copydoc gen6_hiz_exec() */ static void gen7_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt, unsigned int level, unsigned int layer, enum gen6_hiz_op op) { struct gl_context *ctx = &intel->ctx; struct brw_context *brw = brw_context(ctx); assert(op != GEN6_HIZ_OP_DEPTH_CLEAR); /* Not implemented yet. */ assert(mt->hiz_mt != NULL); intel_miptree_check_level_layer(mt, level, layer); uint32_t depth_format; switch (mt->format) { case MESA_FORMAT_Z16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break; case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break; case MESA_FORMAT_X8_Z24: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break; default: assert(0); break; } gen6_hiz_emit_batch_head(brw); gen6_hiz_emit_vertices(brw, mt, level, layer); /* 3DSTATE_URB_VS * 3DSTATE_URB_HS * 3DSTATE_URB_DS * 3DSTATE_URB_GS * * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS: * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be * programmed in order for the programming of this state to be * valid. */ { /* The minimum valid value is 32. See 3DSTATE_URB_VS, * Dword 1.15:0 "VS Number of URB Entries". */ int num_vs_entries = 32; BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2)); OUT_BATCH(1 << GEN7_URB_ENTRY_SIZE_SHIFT | 0 << GEN7_URB_STARTING_ADDRESS_SHIFT | num_vs_entries); ADVANCE_BATCH(); BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2)); OUT_BATCH(0); ADVANCE_BATCH(); BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2)); OUT_BATCH(0); ADVANCE_BATCH(); BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2)); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS * * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. */ { uint32_t depthstencil_offset; gen6_hiz_emit_depth_stencil_state(brw, op, &depthstencil_offset); BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2)); OUT_BATCH(depthstencil_offset | 1); ADVANCE_BATCH(); } /* 3DSTATE_VS * * Disable vertex shader. */ { BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_HS * * Disable the hull shader. */ { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_TE * * Disable the tesselation engine. */ { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_DS * * Disable the domain shader. */ { BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_GS * * Disable the geometry shader. */ { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_STREAMOUT * * Disable streamout. */ { BEGIN_BATCH(3); OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_CLIP * * Disable the clipper. * * The HiZ op emits a rectangle primitive, which requires clipping to * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1 * Section 1.3 "3D Primitives Overview": * RECTLIST: * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip * Mode should be set to a value other than CLIPMODE_NORMAL. * * Also disable perspective divide. This doesn't change the clipper's * output, but does spare a few electrons. */ { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2)); OUT_BATCH(0); OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_SF * * Disable ViewportTransformEnable (dw1.1) * * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D * Primitives Overview": * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the * use of screen- space coordinates). * * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5) * and BackFaceFillMode (dw1.4:3) to SOLID(0). * * From the Sandy Bridge PRM, Volume 2, Part 1, Section * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode: * SOLID: Any triangle or rectangle object found to be front-facing * is rendered as a solid object. This setting is required when * (rendering rectangle (RECTLIST) objects. */ { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2)); OUT_BATCH(depth_format << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_SBE */ { BEGIN_BATCH(14); OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2)); OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */ 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT | 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT); for (int i = 0; i < 12; ++i) OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_WM * * Disable PS thread dispatch (dw1.29) and enable the HiZ op. */ { uint32_t dw1 = 0; switch (op) { case GEN6_HIZ_OP_DEPTH_CLEAR: assert(!"not implemented"); dw1 |= GEN7_WM_DEPTH_CLEAR; break; case GEN6_HIZ_OP_DEPTH_RESOLVE: dw1 |= GEN7_WM_DEPTH_RESOLVE; break; case GEN6_HIZ_OP_HIZ_RESOLVE: dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE; break; default: assert(0); break; } BEGIN_BATCH(3); OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2)); OUT_BATCH(dw1); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_PS * * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite * that, thread dispatch info must still be specified. * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec * states that the valid range for this field is [0x3, 0x2f]. * - A dispatch mode must be given; that is, at least one of the * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was * discovered through simulator error messages. */ { BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(((brw->max_wm_threads - 1) << IVB_PS_MAX_THREADS_SHIFT) | GEN7_PS_32_DISPATCH_ENABLE); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_DEPTH_BUFFER */ { uint32_t width = mt->level[level].width; uint32_t height = mt->level[level].height; uint32_t tile_x; uint32_t tile_y; uint32_t offset; { /* Construct a dummy renderbuffer just to extract tile offsets. */ struct intel_renderbuffer rb; rb.mt = mt; rb.mt_level = level; rb.mt_layer = layer; intel_renderbuffer_set_draw_offset(&rb); offset = intel_renderbuffer_tile_offsets(&rb, &tile_x, &tile_y); } intel_emit_depth_stall_flushes(intel); BEGIN_BATCH(7); OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); OUT_BATCH(((mt->region->pitch * mt->region->cpp) - 1) | depth_format << 18 | 1 << 22 | /* hiz enable */ 1 << 28 | /* depth write */ BRW_SURFACE_2D << 29); OUT_RELOC(mt->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, offset); OUT_BATCH((width + tile_x - 1) << 4 | (height + tile_y - 1) << 18); OUT_BATCH(0); OUT_BATCH(tile_x | tile_y << 16); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_HIER_DEPTH_BUFFER */ { struct intel_region *hiz_region = mt->hiz_mt->region; BEGIN_BATCH(3); OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); OUT_RELOC(hiz_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); ADVANCE_BATCH(); } /* 3DSTATE_STENCIL_BUFFER */ { BEGIN_BATCH(3); OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_CLEAR_PARAMS * * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2 * 3DSTATE_CLEAR_PARAMS: * [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER, * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER). */ { BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DSTATE_DRAWING_RECTANGLE */ { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); OUT_BATCH(0); OUT_BATCH(((mt->level[level].width - 1) & 0xffff) | ((mt->level[level].height - 1) << 16)); OUT_BATCH(0); ADVANCE_BATCH(); } /* 3DPRIMITIVE */ { BEGIN_BATCH(7); OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2)); OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL | _3DPRIM_RECTLIST); OUT_BATCH(3); /* vertex count per instance */ OUT_BATCH(0); OUT_BATCH(1); /* instance count */ OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } /* See comments above at first invocation of intel_flush() in * gen6_hiz_emit_batch_head(). */ intel_flush(ctx); /* Be safe. */ brw->state.dirty.brw = ~0; brw->state.dirty.cache = ~0; }