static irqreturn_t el_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device *dev = dev_id;
struct net_local *lp;
int ioaddr;
int axsr; /* Aux. status reg. */
ioaddr = dev->base_addr;
lp = netdev_priv(dev);
spin_lock(&lp->lock);
/*
* What happened ?
*/
axsr = inb(AX_STATUS);
/*
* Log it
*/
if (el_debug > 3)
printk(KERN_DEBUG "%s: el_interrupt() aux=%#02x", dev->name, axsr);
if(lp->loading==1 && !lp->txing)
printk(KERN_WARNING "%s: Inconsistent state loading while not in tx\n",
dev->name);
if (lp->txing)
{
/*
* Board in transmit mode. May be loading. If we are
* loading we shouldn't have got this.
*/
int txsr = inb(TX_STATUS);
if(lp->loading==1)
{
if(el_debug > 2)
{
printk(KERN_DEBUG "%s: Interrupt while loading [", dev->name);
printk(KERN_DEBUG " txsr=%02x gp=%04x rp=%04x]\n", txsr, inw(GP_LOW),inw(RX_LOW));
}
lp->loading=2; /* Force a reload */
spin_unlock(&lp->lock);
goto out;
}
if (el_debug > 6)
printk(KERN_DEBUG " txsr=%02x gp=%04x rp=%04x", txsr, inw(GP_LOW),inw(RX_LOW));
if ((axsr & 0x80) && (txsr & TX_READY) == 0)
{
/*
* FIXME: is there a logic to whether to keep on trying or
* reset immediately ?
*/
if(el_debug>1)
printk(KERN_DEBUG "%s: Unusual interrupt during Tx, txsr=%02x axsr=%02x"
" gp=%03x rp=%03x.\n", dev->name, txsr, axsr,
inw(ioaddr + EL1_DATAPTR), inw(ioaddr + EL1_RXPTR));
lp->txing = 0;
netif_wake_queue(dev);
}
else if (txsr & TX_16COLLISIONS)
{
/*
* Timed out
*/
if (el_debug)
printk (KERN_DEBUG "%s: Transmit failed 16 times, Ethernet jammed?\n",dev->name);
outb(AX_SYS, AX_CMD);
lp->txing = 0;
lp->stats.tx_aborted_errors++;
netif_wake_queue(dev);
}
else if (txsr & TX_COLLISION)
{
/*
* Retrigger xmit.
*/
if (el_debug > 6)
printk(KERN_DEBUG " retransmitting after a collision.\n");
/*
* Poor little chip can't reset its own start pointer
*/
outb(AX_SYS, AX_CMD);
outw(lp->tx_pkt_start, GP_LOW);
outb(AX_XMIT, AX_CMD);
lp->stats.collisions++;
spin_unlock(&lp->lock);
goto out;
}
else
{
/*
* It worked.. we will now fall through and receive
*/
lp->stats.tx_packets++;
if (el_debug > 6)
printk(KERN_DEBUG " Tx succeeded %s\n",
(txsr & TX_RDY) ? "." : "but tx is busy!");
/*
* This is safe the interrupt is atomic WRT itself.
*/
lp->txing = 0;
netif_wake_queue(dev); /* In case more to transmit */
}
}
else
{
/*
* In receive mode.
*/
int rxsr = inb(RX_STATUS);
if (el_debug > 5)
printk(KERN_DEBUG " rxsr=%02x txsr=%02x rp=%04x", rxsr, inb(TX_STATUS),inw(RX_LOW));
/*
* Just reading rx_status fixes most errors.
*/
if (rxsr & RX_MISSED)
lp->stats.rx_missed_errors++;
else if (rxsr & RX_RUNT)
{ /* Handled to avoid board lock-up. */
lp->stats.rx_length_errors++;
if (el_debug > 5)
printk(KERN_DEBUG " runt.\n");
}
else if (rxsr & RX_GOOD)
{
/*
* Receive worked.
*/
el_receive(dev);
}
else
{
/*
* Nothing? Something is broken!
*/
if (el_debug > 2)
printk(KERN_DEBUG "%s: No packet seen, rxsr=%02x **resetting 3c501***\n",
dev->name, rxsr);
el_reset(dev);
}
if (el_debug > 3)
printk(KERN_DEBUG ".\n");
}
/*
* Move into receive mode
*/
outb(AX_RX, AX_CMD);
outw(0x00, RX_BUF_CLR);
inb(RX_STATUS); /* Be certain that interrupts are cleared. */
inb(TX_STATUS);
spin_unlock(&lp->lock);
out:
return IRQ_HANDLED;
}
void disable_mfgpt0_counter(void)
{
outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
}
static int
ep_eisa_probe(device_t dev)
{
const char *desc;
u_long iobase;
u_short conf;
u_long port;
int irq;
int int_trig;
desc = ep_match(eisa_get_id(dev));
if (!desc)
return (ENXIO);
device_set_desc(dev, desc);
port = (eisa_get_slot(dev) * EISA_SLOT_SIZE);
iobase = port + EP_EISA_SLOT_OFFSET;
/* We must be in EISA configuration mode */
if ((inw(iobase + EP_W0_ADDRESS_CFG) & 0x1f) != 0x1f)
return (ENXIO);
eisa_add_iospace(dev, iobase, EP_EISA_IOSIZE, RESVADDR_NONE);
eisa_add_iospace(dev, port, EP_IOSIZE, RESVADDR_NONE);
conf = inw(iobase + EISA_IOCONF);
/* Determine our IRQ */
switch (conf & IRQ_CHANNEL) {
case INT_3:
irq = 3;
break;
case INT_5:
irq = 5;
break;
case INT_7:
irq = 7;
break;
case INT_9:
irq = 9;
break;
case INT_10:
irq = 10;
break;
case INT_11:
irq = 11;
break;
case INT_12:
irq = 12;
break;
case INT_15:
irq = 15;
break;
default:
/* Disabled */
printf("ep: 3COM Network Adapter at "
"slot %d has its IRQ disabled. "
"Probe failed.\n",
eisa_get_slot(dev));
return (ENXIO);
}
switch (eisa_get_id(dev)) {
case EISA_DEVICE_ID_3COM_3C579_BNC:
case EISA_DEVICE_ID_3COM_3C579_TP:
int_trig = EISA_TRIGGER_LEVEL;
break;
default:
int_trig = EISA_TRIGGER_EDGE;
break;
}
eisa_add_intr(dev, irq, int_trig);
return (0);
}
/* The typical workload of the driver:
Handle the ether interface interrupts. */
static void
el_interrupt(int reg_ptr)
{
int irq = -(((struct pt_regs *)reg_ptr)->orig_eax+2);
/*struct device *dev = (struct device *)(irq2dev_map[irq]);*/
struct device *dev = eldev;
int axsr; /* Aux. status reg. */
short ioaddr;
if (eldev->irq != irq) {
printk (EL_NAME ": irq %d for unknown device\n", irq);
return;
}
ioaddr = dev->base_addr;
axsr = inb(AX_STATUS);
if (el_debug > 3)
printk("%s: el_interrupt() aux=%#02x", dev->name, axsr);
if (dev->interrupt)
printk("%s: Reentering the interrupt driver!\n", dev->name);
dev->interrupt = 1;
if (dev->tbusy) {
int txsr = inb(TX_STATUS);
if (el_debug > 6)
printk(" txsr=%02x gp=%04x rp=%04x", txsr, inw(GP_LOW),
inw(RX_LOW));
if ((axsr & 0x80) && (txsr & TX_READY) == 0) {
printk("%s: Unusual interrupt during Tx, txsr=%02x axsr=%02x"
" gp=%03x rp=%03x.\n", dev->name, txsr, axsr,
inw(ioaddr + EL1_DATAPTR), inw(ioaddr + EL1_RXPTR));
dev->tbusy = 0;
mark_bh(INET_BH);
} else if (txsr & TX_16COLLISIONS) {
if (el_debug)
printk("%s: Transmit failed 16 times, ethernet jammed?\n",
dev->name);
outb(AX_SYS, AX_CMD);
el_status.stats.tx_aborted_errors++;
} else if (txsr & TX_COLLISION) { /* Retrigger xmit. */
if (el_debug > 6)
printk(" retransmitting after a collision.\n");
outb(AX_SYS, AX_CMD);
outw(el_status.tx_pkt_start, GP_LOW);
outb(AX_XMIT, AX_CMD);
el_status.stats.collisions++;
dev->interrupt = 0;
return;
} else {
el_status.stats.tx_packets++;
if (el_debug > 6)
printk(" Tx succeeded %s\n",
(txsr & TX_RDY) ? "." : "but tx is busy!");
dev->tbusy = 0;
mark_bh(INET_BH);
}
} else {
int rxsr = inb(RX_STATUS);
if (el_debug > 5)
printk(" rxsr=%02x txsr=%02x rp=%04x", rxsr, inb(TX_STATUS),
inw(RX_LOW));
/* Just reading rx_status fixes most errors. */
if (rxsr & RX_MISSED)
el_status.stats.rx_missed_errors++;
if (rxsr & RX_RUNT) { /* Handled to avoid board lock-up. */
el_status.stats.rx_length_errors++;
if (el_debug > 5) printk(" runt.\n");
} else if (rxsr & RX_GOOD) {
el_receive(eldev);
} else { /* Nothing? Something is broken! */
if (el_debug > 2)
printk("%s: No packet seen, rxsr=%02x **resetting 3c501***\n",
dev->name, rxsr);
el_reset(eldev);
}
if (el_debug > 3)
printk(".\n");
}
outb(AX_RX, AX_CMD);
outb(0x00, RX_BUF_CLR);
inb(RX_STATUS); /* Be certain that interrupts are cleared. */
inb(TX_STATUS);
dev->interrupt = 0;
return;
}
static struct sal_ret_values
sal_emulator (long index, unsigned long in1, unsigned long in2,
unsigned long in3, unsigned long in4, unsigned long in5,
unsigned long in6, unsigned long in7)
{
long r9 = 0;
long r10 = 0;
long r11 = 0;
long status;
/*
* Don't do a "switch" here since that gives us code that
* isn't self-relocatable.
*/
status = 0;
if (index == SAL_FREQ_BASE) {
switch (in1) {
case SAL_FREQ_BASE_PLATFORM:
r9 = 200000000;
break;
case SAL_FREQ_BASE_INTERVAL_TIMER:
/*
* Is this supposed to be the cr.itc frequency
* or something platform specific? The SAL
* doc ain't exactly clear on this...
*/
r9 = 700000000;
break;
case SAL_FREQ_BASE_REALTIME_CLOCK:
r9 = 1;
break;
default:
status = -1;
break;
}
} else if (index == SAL_SET_VECTORS) {
;
} else if (index == SAL_GET_STATE_INFO) {
;
} else if (index == SAL_GET_STATE_INFO_SIZE) {
;
} else if (index == SAL_CLEAR_STATE_INFO) {
;
} else if (index == SAL_MC_RENDEZ) {
;
} else if (index == SAL_MC_SET_PARAMS) {
;
} else if (index == SAL_CACHE_FLUSH) {
;
} else if (index == SAL_CACHE_INIT) {
;
#ifdef CONFIG_PCI
} else if (index == SAL_PCI_CONFIG_READ) {
/*
* in1 contains the PCI configuration address and in2
* the size of the read. The value that is read is
* returned via the general register r9.
*/
outl(BUILD_CMD(in1), 0xCF8);
if (in2 == 1) /* Reading byte */
r9 = inb(0xCFC + ((REG_OFFSET(in1) & 3)));
else if (in2 == 2) /* Reading word */
r9 = inw(0xCFC + ((REG_OFFSET(in1) & 2)));
else /* Reading dword */
r9 = inl(0xCFC);
status = PCIBIOS_SUCCESSFUL;
} else if (index == SAL_PCI_CONFIG_WRITE) {
/*
* in1 contains the PCI configuration address, in2 the
* size of the write, and in3 the actual value to be
* written out.
*/
outl(BUILD_CMD(in1), 0xCF8);
if (in2 == 1) /* Writing byte */
outb(in3, 0xCFC + ((REG_OFFSET(in1) & 3)));
else if (in2 == 2) /* Writing word */
outw(in3, 0xCFC + ((REG_OFFSET(in1) & 2)));
else /* Writing dword */
outl(in3, 0xCFC);
status = PCIBIOS_SUCCESSFUL;
#endif /* CONFIG_PCI */
} else if (index == SAL_UPDATE_PAL) {
;
} else {
status = -1;
}
return ((struct sal_ret_values) {status, r9, r10, r11});
static void setup_pm(device_t dev)
{
u16 tmp;
/* Debounce LID and PWRBTN# Inputs for 16ms. */
pci_write_config8(dev, 0x80, 0x20);
/* Set ACPI base address to IO VX800_ACPI_IO_BASE */
pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 1);
/* set ACPI irq to 9 */
pci_write_config8(dev, 0x82, 0x49);
/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
// pci_write_config16(dev, 0x84, 0x30f2);
pci_write_config16(dev, 0x84, 0x609a); // 0x609a??
/* SMI output level to low, 7.5us throttle clock */
pci_write_config8(dev, 0x8d, 0x18);
/* GP Timer Control 1s */
pci_write_config8(dev, 0x93, 0x88);
/* Power Well */
pci_write_config8(dev, 0x94, 0x20); // 0x20??
/* 7 = stp to sust delay 1msec
* 6 = SUSST# Deasserted Before PWRGD for STD
*/
pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
/* Disable GP2 & GP3 Timer */
pci_write_config8(dev, 0x98, 0);
/* GP2 Timer Counter */
pci_write_config8(dev, 0x99, 0xfb);
/* GP3 Timer Counter */
//pci_write_config8(dev, 0x9a, 0x20);
/* Multi Function Select 1 */
pci_write_config8(dev, 0xe4, 0x00);
/* Multi Function Select 2 */
pci_write_config8(dev, 0xe5, 0x41); //??
/* Enable ACPI access (and setup like award) */
pci_write_config8(dev, 0x81, 0x84);
/* Clear status events. */
outw(0xffff, VX800_ACPI_IO_BASE + 0x00);
outw(0xffff, VX800_ACPI_IO_BASE + 0x20);
outw(0xffff, VX800_ACPI_IO_BASE + 0x28);
outl(0xffffffff, VX800_ACPI_IO_BASE + 0x30);
/* Disable SCI on GPIO. */
outw(0x0, VX800_ACPI_IO_BASE + 0x22);
/* Disable SMI on GPIO. */
outw(0x0, VX800_ACPI_IO_BASE + 0x24);
/* Disable all global enable SMIs. */
outw(0x0, VX800_ACPI_IO_BASE + 0x2a);
/* All SMI off, both IDE buses ON, PSON rising edge. */
outw(0x0, VX800_ACPI_IO_BASE + 0x2c);
/* Primary activity SMI disable. */
outl(0x0, VX800_ACPI_IO_BASE + 0x34);
/* GP timer reload on none. */
outl(0x0, VX800_ACPI_IO_BASE + 0x38);
/* Disable extended IO traps. */
outb(0x0, VX800_ACPI_IO_BASE + 0x42);
tmp = inw(VX800_ACPI_IO_BASE + 0x04);
/* SCI is generated for RTC/pwrBtn/slpBtn. */
tmp |= 1;
outw(tmp, VX800_ACPI_IO_BASE + 0x04);
/* Allow SLP# signal to assert LDTSTOP_L.
* Will work for C3 and for FID/VID change.
*/
outb(0x1, VX800_ACPI_IO_BASE + 0x11);
/*
outw(0x0, 0x424);
outw(0x0, 0x42a);
outw(0x1, 0x42c);
outl(0x0, 0x434);
outl(0x01, 0x438);
outb(0x0, 0x442);
outl(0xffff7fff, 0x448);
outw(0x001, 0x404);
*/
}
static void S3_lid_wakeup(struct device *dev)
{
outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME
}
/* Initialize IGD OpRegion, called from ACPI code */
int init_igd_opregion(igd_opregion_t *opregion)
{
device_t igd;
u16 reg16;
memset((void *)opregion, 0, sizeof(igd_opregion_t));
// FIXME if IGD is disabled, we should exit here.
memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
sizeof(IGD_OPREGION_SIGNATURE));
/* 8kb */
opregion->header.size = sizeof(igd_opregion_t) / 1024;
opregion->header.version = IGD_OPREGION_VERSION;
// FIXME We just assume we're mobile for now
opregion->header.mailboxes = MAILBOXES_MOBILE;
// TODO Initialize Mailbox 1
// TODO Initialize Mailbox 3
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
init_opregion_vbt(opregion);
/* TODO This needs to happen in S3 resume, too.
* Maybe it should move to the finalize handler
*/
igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
pci_write_config32(igd, ASLS, (u32)opregion);
reg16 = pci_read_config16(igd, SWSCI);
reg16 &= ~(1 << 0);
reg16 |= (1 << 15);
pci_write_config16(igd, SWSCI, reg16);
/* clear dmisci status */
reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
reg16 |= DMISCI_STS; // reference code does an &=
outw(DEFAULT_PMBASE + TCO1_STS, reg16);
/* clear acpi tco status */
outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
/* enable acpi tco scis */
reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
reg16 |= TCOSCI_EN;
outw(DEFAULT_PMBASE + GPE0_EN, reg16);
return 0;
}
int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
{
int i, size;
uint16_t pmbase;
const io_register_t *pm_registers;
struct pci_dev *acpi;
printf("\n============= PMBASE ============\n\n");
switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_3400:
case PCI_DEVICE_ID_INTEL_3420:
case PCI_DEVICE_ID_INTEL_3450:
case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
case PCI_DEVICE_ID_INTEL_3400_MOBILE:
case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
case PCI_DEVICE_ID_INTEL_B55_A:
case PCI_DEVICE_ID_INTEL_B55_B:
case PCI_DEVICE_ID_INTEL_H55:
case PCI_DEVICE_ID_INTEL_H57:
case PCI_DEVICE_ID_INTEL_HM55:
case PCI_DEVICE_ID_INTEL_HM57:
case PCI_DEVICE_ID_INTEL_P55:
case PCI_DEVICE_ID_INTEL_PM55:
case PCI_DEVICE_ID_INTEL_Q57:
case PCI_DEVICE_ID_INTEL_QM57:
case PCI_DEVICE_ID_INTEL_QS57:
case PCI_DEVICE_ID_INTEL_Z68:
case PCI_DEVICE_ID_INTEL_P67:
case PCI_DEVICE_ID_INTEL_UM67:
case PCI_DEVICE_ID_INTEL_HM65:
case PCI_DEVICE_ID_INTEL_H67:
case PCI_DEVICE_ID_INTEL_HM67:
case PCI_DEVICE_ID_INTEL_Q65:
case PCI_DEVICE_ID_INTEL_QS67:
case PCI_DEVICE_ID_INTEL_Q67:
case PCI_DEVICE_ID_INTEL_QM67:
case PCI_DEVICE_ID_INTEL_B65:
case PCI_DEVICE_ID_INTEL_C202:
case PCI_DEVICE_ID_INTEL_C204:
case PCI_DEVICE_ID_INTEL_C206:
case PCI_DEVICE_ID_INTEL_H61:
case PCI_DEVICE_ID_INTEL_Z77:
case PCI_DEVICE_ID_INTEL_Z75:
case PCI_DEVICE_ID_INTEL_Q77:
case PCI_DEVICE_ID_INTEL_Q75:
case PCI_DEVICE_ID_INTEL_B75:
case PCI_DEVICE_ID_INTEL_H77:
case PCI_DEVICE_ID_INTEL_C216:
case PCI_DEVICE_ID_INTEL_QM77:
case PCI_DEVICE_ID_INTEL_QS77:
case PCI_DEVICE_ID_INTEL_HM77:
case PCI_DEVICE_ID_INTEL_UM77:
case PCI_DEVICE_ID_INTEL_HM76:
case PCI_DEVICE_ID_INTEL_HM75:
case PCI_DEVICE_ID_INTEL_HM70:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = pch_pm_registers;
size = ARRAY_SIZE(pch_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH10R:
pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = ich10_pm_registers;
size = ARRAY_SIZE(ich10_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH7:
case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH:
case PCI_DEVICE_ID_INTEL_NM10:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich7_pm_registers;
size = ARRAY_SIZE(ich7_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH9DH:
case PCI_DEVICE_ID_INTEL_ICH9DO:
case PCI_DEVICE_ID_INTEL_ICH9R:
case PCI_DEVICE_ID_INTEL_ICH9:
case PCI_DEVICE_ID_INTEL_ICH9M:
case PCI_DEVICE_ID_INTEL_ICH9ME:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich9_pm_registers;
size = ARRAY_SIZE(ich9_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH8:
case PCI_DEVICE_ID_INTEL_ICH8M:
case PCI_DEVICE_ID_INTEL_ICH8ME:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich8_pm_registers;
size = ARRAY_SIZE(ich8_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH6:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich6_pm_registers;
size = ARRAY_SIZE(ich6_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH5:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich5_pm_registers;
size = ARRAY_SIZE(ich5_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH4:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich4_pm_registers;
size = ARRAY_SIZE(ich4_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH2:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich2_pm_registers;
size = ARRAY_SIZE(ich2_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_ICH0:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich0_pm_registers;
size = ARRAY_SIZE(ich0_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_82371XX:
acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 3);
if (!acpi) {
printf("Southbridge function 3 not found.\n");
return 1;
}
pmbase = pci_read_word(acpi, 0x40) & 0xfffc;
pm_registers = i82371xx_pm_registers;
size = ARRAY_SIZE(i82371xx_pm_registers);
break;
case PCI_DEVICE_ID_INTEL_I63XX:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = i63xx_pm_registers;
size = ARRAY_SIZE(i63xx_pm_registers);
break;
case 0x1234: // Dummy for non-existent functionality
printf("This southbridge does not have PMBASE.\n");
return 1;
default:
printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n");
return 1;
}
printf("PMBASE = 0x%04x (IO)\n\n", pmbase);
for (i = 0; i < size; i++) {
switch (pm_registers[i].size) {
case 8:
printf("pmbase+0x%04x: 0x%08x (%s)\n"
" 0x%08x\n",
pm_registers[i].addr,
inl(pmbase+pm_registers[i].addr),
pm_registers[i].name,
inl(pmbase+pm_registers[i].addr+4));
break;
case 4:
printf("pmbase+0x%04x: 0x%08x (%s)\n",
pm_registers[i].addr,
inl(pmbase+pm_registers[i].addr),
pm_registers[i].name);
break;
case 2:
printf("pmbase+0x%04x: 0x%04x (%s)\n",
pm_registers[i].addr,
inw(pmbase+pm_registers[i].addr),
pm_registers[i].name);
break;
case 1:
printf("pmbase+0x%04x: 0x%02x (%s)\n",
pm_registers[i].addr,
inb(pmbase+pm_registers[i].addr),
pm_registers[i].name);
break;
}
}
return 0;
}
static unsigned short sk_isa_sifreadw(struct net_device *dev, unsigned short reg)
{
return inw(dev->base_addr + reg);
}
static u16 ide_inw (unsigned long port)
{
return (u16) inw(port);
}
static inline u_short
Read_hfc16(hfc4s8s_hw * a, u_char b)
{
SetRegAddr(a, b);
return (inw((volatile u_int) a->iobase));
}
/* Set or clear the multicast filter for this adaptor.
*/
static void
set_multicast_list(struct net_device *dev)
{
struct eepro_local *lp = netdev_priv(dev);
short ioaddr = dev->base_addr;
unsigned short mode;
struct netdev_hw_addr *ha;
int mc_count = netdev_mc_count(dev);
if (dev->flags&(IFF_ALLMULTI|IFF_PROMISC) || mc_count > 63)
{
eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */
mode = inb(ioaddr + REG2);
outb(mode | PRMSC_Mode, ioaddr + REG2);
mode = inb(ioaddr + REG3);
outb(mode, ioaddr + REG3); /* writing reg. 3 to complete the update */
eepro_sw2bank0(ioaddr); /* Return to BANK 0 now */
}
else if (mc_count == 0)
{
eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */
mode = inb(ioaddr + REG2);
outb(mode & 0xd6, ioaddr + REG2); /* Turn off Multi-IA and PRMSC_Mode bits */
mode = inb(ioaddr + REG3);
outb(mode, ioaddr + REG3); /* writing reg. 3 to complete the update */
eepro_sw2bank0(ioaddr); /* Return to BANK 0 now */
}
else
{
unsigned short status, *eaddrs;
int i, boguscount = 0;
/* Disable RX and TX interrupts. Necessary to avoid
corruption of the HOST_ADDRESS_REG by interrupt
service routines. */
eepro_dis_int(ioaddr);
eepro_sw2bank2(ioaddr); /* be CAREFUL, BANK 2 now */
mode = inb(ioaddr + REG2);
outb(mode | Multi_IA, ioaddr + REG2);
mode = inb(ioaddr + REG3);
outb(mode, ioaddr + REG3); /* writing reg. 3 to complete the update */
eepro_sw2bank0(ioaddr); /* Return to BANK 0 now */
outw(lp->tx_end, ioaddr + HOST_ADDRESS_REG);
outw(MC_SETUP, ioaddr + IO_PORT);
outw(0, ioaddr + IO_PORT);
outw(0, ioaddr + IO_PORT);
outw(6 * (mc_count + 1), ioaddr + IO_PORT);
netdev_for_each_mc_addr(ha, dev) {
eaddrs = (unsigned short *) ha->addr;
outw(*eaddrs++, ioaddr + IO_PORT);
outw(*eaddrs++, ioaddr + IO_PORT);
outw(*eaddrs++, ioaddr + IO_PORT);
}
eaddrs = (unsigned short *) dev->dev_addr;
outw(eaddrs[0], ioaddr + IO_PORT);
outw(eaddrs[1], ioaddr + IO_PORT);
outw(eaddrs[2], ioaddr + IO_PORT);
outw(lp->tx_end, ioaddr + lp->xmt_bar);
outb(MC_SETUP, ioaddr);
/* Update the transmit queue */
i = lp->tx_end + XMT_HEADER + 6 * (mc_count + 1);
if (lp->tx_start != lp->tx_end)
{
/* update the next address and the chain bit in the
last packet */
outw(lp->tx_last + XMT_CHAIN, ioaddr + HOST_ADDRESS_REG);
outw(i, ioaddr + IO_PORT);
outw(lp->tx_last + XMT_COUNT, ioaddr + HOST_ADDRESS_REG);
status = inw(ioaddr + IO_PORT);
outw(status | CHAIN_BIT, ioaddr + IO_PORT);
lp->tx_end = i ;
}
else {
lp->tx_start = lp->tx_end = i ;
}
/* Acknowledge that the MC setup is done */
do { /* We should be doing this in the eepro_interrupt()! */
SLOW_DOWN;
SLOW_DOWN;
if (inb(ioaddr + STATUS_REG) & 0x08)
{
i = inb(ioaddr);
outb(0x08, ioaddr + STATUS_REG);
if (i & 0x20) { /* command ABORTed */
printk(KERN_NOTICE "%s: multicast setup failed.\n",
dev->name);
break;
} else if ((i & 0x0f) == 0x03) { /* MC-Done */
printk(KERN_DEBUG "%s: set Rx mode to %d address%s.\n",
dev->name, mc_count,
mc_count > 1 ? "es":"");
break;
}
}
} while (++boguscount < 100);
/* Re-enable RX and TX interrupts */
eepro_en_int(ioaddr);
}
static int __init init_hs(void)
{
servinfo_t serv;
int i;
unsigned short v;
/*
* Check API version
*/
pcmcia_get_card_services_info(&serv);
if (serv.Revision != CS_RELEASE_CODE) {
printk(KERN_NOTICE MODNAME ": Card Services release does not match!\n");
return -ENODEV;
}
/* hd64465_io_debug = 1; */
/* Wake both sockets out of STANDBY mode */
/* TODO: wait 15ms */
v = inw(HD64465_REG_SMSCR);
v &= ~(HD64465_SMSCR_PC0ST|HD64465_SMSCR_PC1ST);
outw(v, HD64465_REG_SMSCR);
/* keep power controller out of shutdown mode */
v = inb(HD64465_REG_PCC0SCR);
v |= HD64465_PCCSCR_SHDN;
outb(v, HD64465_REG_PCC0SCR);
/* use serial (TPS2206) power controller */
v = inb(HD64465_REG_PCC0CSCR);
v |= HD64465_PCCCSCR_PSWSEL;
outb(v, HD64465_REG_PCC0CSCR);
hs_set_voltages(&hs_sockets[0], 0, 0);
hs_set_voltages(&hs_sockets[1], 0, 0);
/*
* Setup hs_sockets[] structures and request system resources.
* TODO: on memory allocation failure, power down the socket
* before quitting.
*/
i = hs_init_socket(&hs_sockets[0],
HD64465_IRQ_PCMCIA0,
HD64465_PCC0_BASE,
HD64465_REG_PCC0ISR);
if (i < 0)
return i;
i = hs_init_socket(&hs_sockets[1],
HD64465_IRQ_PCMCIA1,
HD64465_PCC1_BASE,
HD64465_REG_PCC1ISR);
if (i < 0)
return i;
/* hd64465_io_debug = 0; */
if (register_ss_entry(HS_MAX_SOCKETS, &hs_operations) != 0) {
for (i=0 ; i<HS_MAX_SOCKETS ; i++)
hs_exit_socket(&hs_sockets[i]);
return -ENODEV;
}
printk(KERN_INFO "HD64465 PCMCIA bridge:\n");
for (i=0 ; i<HS_MAX_SOCKETS ; i++) {
hs_socket_t *sp = &hs_sockets[i];
printk(KERN_INFO " socket %d at 0x%08lx irq %d io window %ldK@0x%08lx\n",
i, sp->mem_base, sp->irq,
sp->io_vma->size>>10, (unsigned long)sp->io_vma->addr);
}
return 0;
}
static unsigned short pcibios_read_config_word(
unsigned char bus, unsigned devfn, unsigned where)
{
outl(config_cmd(bus, devfn, where), 0xCF8);
return inw(0xCFC + (where & 2));
}
u16
uhci_reg_read16 (hci_t *ctrl, usbreg reg)
{
return inw (ctrl->reg_base + reg);
}
static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
return inw(0xcfc);
}
static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
{
int i2c_error = 0;
u16 status;
/* wait until bus not busy */
wait_for_bb ();
/* one byte only */
outw (1, I2C_CNT);
/* set slave address */
outw (devaddr, I2C_SA);
/* no stop bit needed here */
outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON);
status = wait_for_pin ();
if (status & I2C_STAT_XRDY) {
/* Important: have to use byte access */
*(volatile u8 *) (I2C_DATA) = regoffset;
udelay (20000);
if (inw (I2C_STAT) & I2C_STAT_NACK) {
i2c_error = 1;
}
} else {
i2c_error = 1;
}
if (!i2c_error) {
/* free bus, otherwise we can't use a combined transction */
outw (0, I2C_CON);
while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) {
udelay (10000);
/* Have to clear pending interrupt to clear I2C_STAT */
outw (0xFFFF, I2C_STAT);
}
wait_for_bb ();
/* set slave address */
outw (devaddr, I2C_SA);
/* read one byte from slave */
outw (1, I2C_CNT);
/* need stop bit here */
outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
I2C_CON);
status = wait_for_pin ();
if (status & I2C_STAT_RRDY) {
*value = inw (I2C_DATA);
udelay (20000);
} else {
i2c_error = 1;
}
if (!i2c_error) {
outw (I2C_CON_EN, I2C_CON);
while (inw (I2C_STAT)
|| (inw (I2C_CON) & I2C_CON_MST)) {
udelay (10000);
outw (0xFFFF, I2C_STAT);
}
}
}
flush_fifo();
outw (0xFFFF, I2C_STAT);
outw (0, I2C_CNT);
return i2c_error;
}
static void S3_usb_wakeup(struct device *dev)
{
outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME
}
static void omap1610_audio_init(void *dummy)
{
u16 tmp;
FN_IN;
/* check that open mode is correct */
if(openMode & FMODE_WRITE || openMode & FMODE_READ){
}else{
printk("Incorrect open mode: %s:%d %s\n",__FILE__,__LINE__,__FUNCTION__);
FN_OUT(1);
return;
}
/*
Now here's an ugly hack. To use McBSP1, you need to enable
a clock on the DSP. So enable the MPUI, set the clock,
and start the DSP.
An even uglier, evil hack. If this is going to take the DSP
out of reset, shove an idle loop at the reset vector
and make it loop instead of crash. You will still see
a DSP watchdog timer go off.
I would prefer having a DSP program (probably the MP3 decoder) set
up the DSP, but this allows an ARM-only MP3 decoder to work. With
this code, the DSP is never put into idle, so the OMAP chip cannot
go into any decent low-power mode. Also, all of the DSP interface
dependencies (such as MPUI_STROBE settings) would be taken care
of. Plus, we wouldn't have to worry about different boot vector
addresses depending on the chip version.
*/
{
u32 boot_vector;
u8 c55_start[] = { 0x7A, 0x00, 0x00, 0x0C, 0x4A, 0x7A, 0x20, 0x20, 0x20, 0x20 };
tmp = inw(0xfffece10); /* read ARM_RSTCT1 register */
if (0 == (tmp & 0x6)) { /* check if DSP is up */
DPRINTK(__FUNCTION__ ": Bringing DSP out of reset.\n");
if (0 == (tmp & 0x4)) { /* MPUI in reset */
tmp |= 0x4;
outw(tmp, 0xfffece10);
ck_enable(api_ck);
}
tmp = inw(0xe1008008); /* read DSP_IDLECT2 register */
if (6 != (tmp & 0x6)) { /* DSP CLKM enable */
tmp |= 0x6;
outw(tmp, 0xe1008008);
}
tmp = inw(0xe1008014); /* read DSP_RSTCT2 register */
if (3 != (tmp & 0x3)) { /* DSP PER_EN bit */
tmp |= 0x3;
outw(tmp, 0xe1008014);
}
tmp = inw(0xfffece00); /* read ARM_CKCTL register */
tmp |= 0x2000;
outw(tmp, 0xfffece00);
/* Write C55 code at reset vector. */
DPRINTK(__FUNCTION__ ": Bringing DSP out of reset - in progress.\n");
boot_vector = 0x10000;
memcpy((void *)(OMAP_DSP_BASE + boot_vector),
&c55_start,
sizeof(c55_start));
outw(0x5, 0xfffec918); /* Set DSP boot mode */
tmp = inw(0xfffece10); /* take DSP out of reset */
tmp |= 0x6;
outw(tmp, 0xfffece10);
}
else { /* DSP's up, just check the clock/per bits */
tmp = inw(0xe1008008);
if (0 == (tmp & 0x2)) { /* DSP CLKM enable */
tmp |= 0x2;
outw(tmp, 0xe1008008);
}
tmp = inw(0xe1008014);
if (0 == (tmp & 0x1)) { /* DSP PER_EN bit */
tmp |= 0x1;
outw(tmp, 0xe1008014);
}
}
}
/*
Configure the DMA channel and MCBSP.
*/
DPRINTK(__FUNCTION__ ": Configure DMA output channel. output_stream.dma_regs: %p\n", output_stream.dma_regs);
DPRINTK(__FUNCTION__ ": Configure DMA input channel. input_stream.dma_regs: %p\n", input_stream.dma_regs);
if(openMode & FMODE_WRITE){
/* Setup DMA channel to McBSP1 audio Tx. */
output_stream.dma_regs->csdp = 0x0a01;
output_stream.dma_regs->ccr |= 0x1400;/* !!!!! source auto increment, don't enable yet */
output_stream.dma_regs->cicr = 0x23;
output_stream.dma_regs->cdsa_l = ((OMAP1610_MCBSP1_BASE + 0x806) & 0xffff); /* McBSP1 DXR1 */
output_stream.dma_regs->cdsa_u = ((OMAP1610_MCBSP1_BASE + 0x806) >> 16);
output_stream.dma_regs->cfn = 0x1;
omap_dma_setup(audio_state.output_stream->dma_dev, eDmaOut);
}/* if(openMode & FMODE_WRITE) */
void pdacf_tasklet(unsigned long private_data)
{
pdacf_t *chip = (pdacf_t *) private_data;
int size, off, cont, rdp, wdp;
if ((chip->chip_status & (PDAUDIOCF_STAT_IS_STALE|PDAUDIOCF_STAT_IS_CONFIGURED)) != PDAUDIOCF_STAT_IS_CONFIGURED)
return;
if (chip->pcm_substream == NULL || chip->pcm_substream->runtime == NULL || !snd_pcm_running(chip->pcm_substream))
return;
rdp = inw(chip->port + PDAUDIOCF_REG_RDP);
wdp = inw(chip->port + PDAUDIOCF_REG_WDP);
// printk("TASKLET: rdp = %x, wdp = %x\n", rdp, wdp);
size = wdp - rdp;
if (size < 0)
size += 0x10000;
if (size == 0)
size = 0x10000;
size /= chip->pcm_frame;
if (size > 64)
size -= 32;
#if 0
chip->pcm_hwptr += size;
chip->pcm_hwptr %= chip->pcm_size;
chip->pcm_tdone += size;
if (chip->pcm_frame == 2) {
unsigned long rdp_port = chip->port + PDAUDIOCF_REG_MD;
while (size-- > 0) {
inw(rdp_port);
inw(rdp_port);
}
} else {
unsigned long rdp_port = chip->port + PDAUDIOCF_REG_MD;
while (size-- > 0) {
inw(rdp_port);
inw(rdp_port);
inw(rdp_port);
}
}
#else
off = chip->pcm_hwptr + chip->pcm_tdone;
off %= chip->pcm_size;
chip->pcm_tdone += size;
while (size > 0) {
cont = chip->pcm_size - off;
if (cont > size)
cont = size;
pdacf_transfer(chip, cont, off);
off += cont;
off %= chip->pcm_size;
size -= cont;
}
#endif
spin_lock(&chip->reg_lock);
while (chip->pcm_tdone >= chip->pcm_period) {
chip->pcm_hwptr += chip->pcm_period;
chip->pcm_hwptr %= chip->pcm_size;
chip->pcm_tdone -= chip->pcm_period;
spin_unlock(&chip->reg_lock);
snd_pcm_period_elapsed(chip->pcm_substream);
spin_lock(&chip->reg_lock);
}
spin_unlock(&chip->reg_lock);
// printk("TASKLET: end\n");
}
/* ne2000_init --------------------------------------------------------------*/
void
ne2000_init()
{
int i;
/*
int sendq_nr;
int offset_page;
int ramsize;
short s;
*/
/* stop remote DMA */
outb(IO_DP8390 + DP_CR, CR_DM_ABORT | CR_STP);
#if 0
/* FIFO */
outb(IO_DP8390 + DP_DCR, DCR_8BYTES | DCR_WORDWIDE | DCR_BMS);
#else
outb(IO_DP8390 + DP_DCR, DCR_8BYTES | DCR_BYTEWIDE | DCR_BMS);
#endif
/* clear DMA byte count */
outb(IO_DP8390 + DP_RBCR0, 0);
outb(IO_DP8390 + DP_RBCR1, 0);
/* monitor mode */
outb(IO_DP8390 + DP_RCR, RCR_MON);
/* internal loopback mode */
outb(IO_DP8390 + DP_TCR, TCR_INTERNAL);
/* specify ring buffer of start address for transfering */
outb(IO_DP8390 + DP_TSR, PAGE_TX_START);
outb(IO_DP8390 + DP_PSTART, PAGE_RX_START);
outb(IO_DP8390 + DP_BNRY, PAGE_RX_START);
outb(IO_DP8390 + DP_PSTOP, PAGE_END);
/* clear interrupt flag */
outb(IO_DP8390 + DP_ISR, 0xff);
/* configure enabling interrupt */
outb(IO_DP8390 + DP_IMR, IMR_PRXE);
#if 1
/* old code start ---------------------------------------------------*/
outb(IO_DP8390 + DP_RBCR0, 6 * 2);
outb(IO_DP8390 + DP_RBCR1, 0);
outb(IO_DP8390 + DP_RSAR0, 0);
outb(IO_DP8390 + DP_RSAR1, 0);
outb(IO_DP8390 + DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
/* Mmm... card is 8bit ??? ne1000 ??? */
printk("Ethernet = ");
for (i = 0 ; i < 5 ; i ++) {
ed.ether[i] = (char)inw(IO_NE2000 + NE_DATA) & 0xff;
printk("%x:", ed.ether[i]);
}
ed.ether[i] = (char)inw(IO_NE2000 + NE_DATA) & 0xff;
printk("%x\n", ed.ether[i]);
/* old code end -----------------------------------------------------*/
#endif
/* configure page 1 */
outb(IO_DP8390 + DP_CR, CR_DM_ABORT | CR_PS_P1 | CR_STP);
/* set up ethernet address */
#if 1
outb(IO_DP8390 + DP_PAR0, ed.ether[0]);
outb(IO_DP8390 + DP_PAR1, ed.ether[1]);
outb(IO_DP8390 + DP_PAR2, ed.ether[2]);
outb(IO_DP8390 + DP_PAR3, ed.ether[3]);
outb(IO_DP8390 + DP_PAR4, ed.ether[4]);
outb(IO_DP8390 + DP_PAR5, ed.ether[5]);
#else
outb(IO_DP8390 + DP_PAR0, 0x00);
outb(IO_DP8390 + DP_PAR1, 0xe0);
outb(IO_DP8390 + DP_PAR2, 0x98);
outb(IO_DP8390 + DP_PAR3, 0x16);
outb(IO_DP8390 + DP_PAR4, 0x06);
outb(IO_DP8390 + DP_PAR5, 0x66);
#endif
/* set up page number for first received packet */
outb(IO_DP8390 + DP_CURR, PAGE_RX_START + 1);
/* set up muiticast register */
outb(IO_DP8390 + DP_MAR0, 0);
outb(IO_DP8390 + DP_MAR1, 0);
outb(IO_DP8390 + DP_MAR2, 0);
outb(IO_DP8390 + DP_MAR3, 0);
outb(IO_DP8390 + DP_MAR4, 0);
outb(IO_DP8390 + DP_MAR5, 0);
outb(IO_DP8390 + DP_MAR6, 0);
outb(IO_DP8390 + DP_MAR7, 0);
/* configure page 1 */
outb(IO_DP8390 + DP_CR, CR_DM_ABORT | CR_STP);
#if 0
/* promiscious mode -------------------------------------------------*/
outb(IO_DP8390 + DP_RCR, RCR_AB | RCR_PRO | RCR_AM
| RCR_AB | RCR_AM);
#else
/* normal mode (broadcast + multicast) ------------------------------*/
/* setup filtering for received packet */
outb(IO_DP8390 + DP_RCR, RCR_AB | RCR_AM);
#endif
#if 1
/* activate NIC */
outb(IO_DP8390 + DP_CR, CR_DM_ABORT | CR_STA);
/* enter normal mode */
outb(IO_DP8390 + DP_TCR, 0);
#else
inb(IO_DP8390 + DP_CNTR0);
inb(IO_DP8390 + DP_CNTR1);
inb(IO_DP8390 + DP_CNTR2);
outb(IO_DP8390 + DP_IMR, IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE |
IMR_OVWE | IMR_CNTE);
outb(IO_DP8390 + DP_CR, CR_STA | CR_DM_ABORT);
outb(IO_DP8390 + DP_TCR, 0);
#endif
#if 0
offset_page = NE2000_START / DP_PAGESIZE;
ramsize = NE2000_SIZE;
sendq_nr = NE2000_SIZE / 0x2000;
ed.sendpage = offset_page;
/* dp8390 initialization --------------------------------------------*/
outb(IO_DP8390 + DP_CR, CR_PS_P0 | CR_STP | CR_DM_ABORT);
outb(IO_DP8390 + DP_IMR, 0);
outb(IO_DP8390 + DP_PSTART, offset_page + sendq_nr * SENDQ_PAGES);
ed.startpage = offset_page + sendq_nr * SENDQ_PAGES;
outb(IO_DP8390 + DP_PSTOP, offset_page + ramsize / DP_PAGESIZE);
ed.stoppage = offset_page + ramsize / DP_PAGESIZE;
outb(IO_DP8390 + DP_BNRY, offset_page + sendq_nr * SENDQ_PAGES);
outb(IO_DP8390 + DP_RCR, RCR_MON);
outb(IO_DP8390 + DP_TCR, TCR_NORMAL);
#if 0
/* 16 bit */
outb(IO_DP8390 + DP_DCR, DCR_WORDWIDE | DCR_8BYTES | DCR_BMS);
#else
/* 8 bit */
outb(IO_DP8390 + DP_DCR, DCR_BYTEWIDE | DCR_8BYTES | DCR_BMS);
#endif
outb(IO_DP8390 + DP_RBCR0, 0);
outb(IO_DP8390 + DP_RBCR1, 0);
outb(IO_DP8390 + DP_ISR, 0xff);
outb(IO_DP8390 + DP_CR, CR_PS_P1 | CR_DM_ABORT);
outb(IO_DP8390 + DP_PAR0, ed.ether[0]);
outb(IO_DP8390 + DP_PAR1, ed.ether[1]);
outb(IO_DP8390 + DP_PAR2, ed.ether[2]);
outb(IO_DP8390 + DP_PAR3, ed.ether[3]);
outb(IO_DP8390 + DP_PAR4, ed.ether[4]);
outb(IO_DP8390 + DP_PAR5, ed.ether[5]);
outb(IO_DP8390 + DP_MAR0, 0xff);
outb(IO_DP8390 + DP_MAR1, 0xff);
outb(IO_DP8390 + DP_MAR2, 0xff);
outb(IO_DP8390 + DP_MAR3, 0xff);
outb(IO_DP8390 + DP_MAR4, 0xff);
outb(IO_DP8390 + DP_MAR5, 0xff);
outb(IO_DP8390 + DP_MAR6, 0xff);
outb(IO_DP8390 + DP_MAR7, 0xff);
outb(IO_DP8390 + DP_CURR, offset_page + sendq_nr * SENDQ_PAGES + 1);
outb(IO_DP8390 + DP_CR, CR_PS_P0 | CR_DM_ABORT);
#if 0
/* promiscious ------------------------------------------------------*/
outb(IO_DP8390 + DP_RCR, RCR_AB | RCR_PRO | RCR_AM
| RCR_AB | RCR_AM);
/* promiscious ------------------------------------------------------*/
#else
outb(IO_DP8390 + DP_RCR, RCR_AB);
#endif
inb(IO_DP8390 + DP_CNTR0);
inb(IO_DP8390 + DP_CNTR1);
inb(IO_DP8390 + DP_CNTR2);
outb(IO_DP8390 + DP_IMR, IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE |
IMR_OVWE | IMR_CNTE);
outb(IO_DP8390 + DP_CR, CR_STA | CR_DM_ABORT);
#endif
printk("ne2000: initialized\n");
}
/* ----------------------------------------------------------------------------
mace_rx
Receives packets.
---------------------------------------------------------------------------- */
static int mace_rx(struct net_device *dev, unsigned char RxCnt)
{
mace_private *lp = netdev_priv(dev);
unsigned int ioaddr = dev->base_addr;
unsigned char rx_framecnt;
unsigned short rx_status;
while (
((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
(rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
(RxCnt--)
) {
rx_status = inw(ioaddr + AM2150_RCV);
pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
" 0x%X.\n", dev->name, rx_framecnt, rx_status);
if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
lp->linux_stats.rx_errors++;
if (rx_status & MACE_RCVFS_OFLO) {
lp->mace_stats.oflo++;
}
if (rx_status & MACE_RCVFS_CLSN) {
lp->mace_stats.clsn++;
}
if (rx_status & MACE_RCVFS_FRAM) {
lp->mace_stats.fram++;
}
if (rx_status & MACE_RCVFS_FCS) {
lp->mace_stats.fcs++;
}
} else {
short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
/* Auto Strip is off, always subtract 4 */
struct sk_buff *skb;
lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
/* runt packet count */
lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
/* rcv collision count */
pr_debug(" receiving packet size 0x%X rx_status"
" 0x%X.\n", pkt_len, rx_status);
skb = dev_alloc_skb(pkt_len+2);
if (skb != NULL) {
skb_reserve(skb, 2);
insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
if (pkt_len & 1)
*(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
skb->protocol = eth_type_trans(skb, dev);
netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
lp->linux_stats.rx_packets++;
lp->linux_stats.rx_bytes += pkt_len;
outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
continue;
} else {
pr_debug("%s: couldn't allocate a sk_buff of size"
" %d.\n", dev->name, pkt_len);
lp->linux_stats.rx_dropped++;
}
}
static void InitBoard(struct IBMLANA_NETDEV *dev)
{
int camcnt;
camentry_t cams[16];
u32 cammask;
struct dev_mc_list *mcptr;
u16 rcrval;
/* reset the SONIC */
outw(CMDREG_RST, dev->base_addr + SONIC_CMDREG);
udelay(10);
/* clear all spurious interrupts */
outw(inw(dev->base_addr + SONIC_ISREG),
dev->base_addr + SONIC_ISREG);
/* set up the SONIC's bus interface - constant for this adapter -
must be done while the SONIC is in reset */
outw(DCREG_USR1 | DCREG_USR0 | DCREG_WC1 | DCREG_DW32,
dev->base_addr + SONIC_DCREG);
outw(0, dev->base_addr + SONIC_DCREG2);
/* remove reset form the SONIC */
outw(0, dev->base_addr + SONIC_CMDREG);
udelay(10);
/* data sheet requires URRA to be programmed before setting up the CAM contents */
outw(0, dev->base_addr + SONIC_URRA);
/* program the CAM entry 0 to the device address */
camcnt = 0;
putcam(cams, &camcnt, dev->dev_addr);
/* start putting the multicast addresses into the CAM list. Stop if
it is full. */
for (mcptr = dev->mc_list; mcptr != NULL; mcptr = mcptr->next) {
putcam(cams, &camcnt, mcptr->dmi_addr);
if (camcnt == 16)
break;
}
/* calculate CAM mask */
cammask = (1 << camcnt) - 1;
/* feed CDA into SONIC, initialize RCR value (always get broadcasts) */
IBMLANA_TOIO(dev->mem_start, cams, sizeof(camentry_t) * camcnt);
IBMLANA_TOIO(dev->mem_start + (sizeof(camentry_t) * camcnt),
&cammask, sizeof(cammask));
#ifdef DEBUG
printk("CAM setup:\n");
dumpmem(dev, 0, sizeof(camentry_t) * camcnt + sizeof(cammask));
#endif
outw(0, dev->base_addr + SONIC_CAMPTR);
outw(camcnt, dev->base_addr + SONIC_CAMCNT);
outw(CMDREG_LCAM, dev->base_addr + SONIC_CMDREG);
if (!wait_timeout(dev, SONIC_CMDREG, CMDREG_LCAM, 0, 2)) {
printk
("%s:SONIC did not respond on LCAM command - giving up.",
dev->name);
return;
} else {
/* clear interrupt condition */
outw(ISREG_LCD, dev->base_addr + SONIC_ISREG);
#ifdef DEBUG
printk("Loading CAM done, address pointers %04x:%04x\n",
inw(dev->base_addr + SONIC_URRA),
inw(dev->base_addr + SONIC_CAMPTR));
{
int z;
printk("\n-->CAM: PTR %04x CNT %04x\n",
inw(dev->base_addr + SONIC_CAMPTR),
inw(dev->base_addr + SONIC_CAMCNT));
outw(CMDREG_RST, dev->base_addr + SONIC_CMDREG);
for (z = 0; z < camcnt; z++) {
outw(z, dev->base_addr + SONIC_CAMEPTR);
printk("Entry %d: %04x %04x %04x\n", z,
inw(dev->base_addr +
SONIC_CAMADDR0),
inw(dev->base_addr +
SONIC_CAMADDR1),
inw(dev->base_addr +
SONIC_CAMADDR2));
}
outw(0, dev->base_addr + SONIC_CMDREG);
}
#endif
}
rcrval = RCREG_BRD | RCREG_LB_NONE;
/* if still multicast addresses left or ALLMULTI is set, set the multicast
enable bit */
if ((dev->flags & IFF_ALLMULTI) || (mcptr != NULL))
rcrval |= RCREG_AMC;
/* promiscous mode ? */
if (dev->flags & IFF_PROMISC)
rcrval |= RCREG_PRO;
/* program receive mode */
outw(rcrval, dev->base_addr + SONIC_RCREG);
#ifdef DEBUG
printk("\nRCRVAL: %04x\n", rcrval);
#endif
/* set up descriptors in shared memory + feed them into SONIC registers */
InitDscrs(dev);
if (!InitSONIC(dev))
return;
/* reset all pending interrupts */
outw(0xffff, dev->base_addr + SONIC_ISREG);
/* enable transmitter + receiver interrupts */
outw(CMDREG_RXEN, dev->base_addr + SONIC_CMDREG);
outw(IMREG_PRXEN | IMREG_RBEEN | IMREG_PTXEN | IMREG_TXEREN,
dev->base_addr + SONIC_IMREG);
/* turn on card interrupts */
outb(inb(dev->base_addr + BCMREG) | BCMREG_IEN,
dev->base_addr + BCMREG);
#ifdef DEBUG
printk("Register dump after initialization:\n");
dumpregs(dev);
#endif
}
static unsigned int ioport_read16(void __iomem *addr)
{
return inw(ADDR2PORT(addr));
}
/*
* Initialize the SnapGear PCI interface
* Setup hardware to be Central Funtion
* Copy the BSR regs to the PCI interface
* Setup PCI windows into local RAM
*/
int __init pcibios_init_platform(void) {
u32 reg;
u32 word;
u32 id;
PCIDBG(1,"PCI: snapgear_pci_init called\n");
/* Set the BCR's to enable PCI access */
reg = inl(SH7751_BCR1);
reg |= 0x80000;
outl(reg, SH7751_BCR1);
/* check for SH7751/SH7751R hardware */
id = inl(SH7751_PCIREG_BASE+SH7751_PCICONF0);
switch (id) {
case (SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID:
printk("PCI: SH7751 PCI host bridge found.\n");
break;
case (SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID:
printk("PCI: SH7751R PCI host bridge found.\n");
break;
default:
printk("PCI: Unknown PCI host bridge (id=0x%x).\n", id);
return(0);
}
/* Turn the clocks back on (not done in reset)*/
outl(0, PCI_REG(SH7751_PCICLKR));
/* Clear Powerdown IRQ's (not done in reset) */
word = SH7751_PCIPINT_D3 | SH7751_PCIPINT_D0;
outl(word, PCI_REG(SH7751_PCICLKR));
#if 0
/*
* This code is removed as it is done in the bootloader and doing it
* here means the MAC addresses loaded by the bootloader get lost
*/
/* toggle PCI reset pin */
word = SH7751_PCICR_PREFIX | SH7751_PCICR_PRST;
outl(word,PCI_REG(SH7751_PCICR));
/* Wait for a long time... not 1 sec. but long enough */
mdelay(100);
word = SH7751_PCICR_PREFIX;
outl(word,PCI_REG(SH7751_PCICR));
#endif
/* set the command/status bits to:
* Wait Cycle Control + Parity Enable + Bus Master +
* Mem space enable
*/
word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
outl(word, PCI_REG(SH7751_PCICONF1));
/* define this host as the host bridge */
word = SH7751_PCI_HOST_BRIDGE << 24;
outl(word, PCI_REG(SH7751_PCICONF2));
/* Set IO and Mem windows to local address
* Make PCI and local address the same for easy 1 to 1 mapping
* Window0 = SNAPGEAR_LSR0_SIZE @ non-cached CS2 base = SDRAM
* Window1 = SNAPGEAR_LSR1_SIZE @ cached CS2 base = SDRAM
*/
word = SNAPGEAR_LSR0_SIZE - 1;
outl(word, PCI_REG(SH7751_PCILSR0));
word = SNAPGEAR_LSR1_SIZE - 1;
outl(word, PCI_REG(SH7751_PCILSR1));
/* Set the values on window 0 PCI config registers */
word = P2SEGADDR(SH7751_CS2_BASE_ADDR);
outl(word, PCI_REG(SH7751_PCILAR0));
outl(word, PCI_REG(SH7751_PCICONF5));
/* Set the values on window 1 PCI config registers */
word = PHYSADDR(SH7751_CS2_BASE_ADDR);
outl(word, PCI_REG(SH7751_PCILAR1));
outl(word, PCI_REG(SH7751_PCICONF6));
/* Set the local 16MB PCI memory space window to
* the lowest PCI mapped address
*/
word = PCIBIOS_MIN_MEM & SH7751_PCIMBR_MASK;
PCIDBG(2,"PCI: Setting upper bits of Memory window to 0x%x\n", word);
outl(word , PCI_REG(SH7751_PCIMBR));
/* Map IO space into PCI IO window
* The IO window is 64K-PCIBIOS_MIN_IO in size
* IO addresses will be translated to the
* PCI IO window base address
*/
PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
(64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO);
/* Make sure the MSB's of IO window are set to access PCI space correctly */
word = PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK;
PCIDBG(2,"PCI: Setting upper bits of IO window to 0x%x\n", word);
outl(word, PCI_REG(SH7751_PCIIOBR));
/* Set PCI WCRx, BCRx's, copy from BSC locations */
word = inl(SH7751_BCR1);
/* check BCR for SDRAM in area 3 */
if(((word >> 2) & 1) == 0) {
printk("PCI: Area 2 is not configured for SDRAM. BCR1=0x%x\n", word);
return 0;
}
outl(word, PCI_REG(SH7751_PCIBCR1));
word = (u16)inw(SH7751_BCR2);
/* check BCR2 for 32bit SDRAM interface*/
if(((word >> 4) & 0x3) != 0x3) {
printk("PCI: Area 2 is not 32 bit SDRAM. BCR2=0x%x\n", word);
return 0;
}
outl(word, PCI_REG(SH7751_PCIBCR2));
/* configure the wait control registers */
word = inl(SH7751_WCR1);
outl(word, PCI_REG(SH7751_PCIWCR1));
word = inl(SH7751_WCR2);
outl(word, PCI_REG(SH7751_PCIWCR2));
word = inl(SH7751_WCR3);
outl(word, PCI_REG(SH7751_PCIWCR3));
word = inl(SH7751_MCR);
outl(word, PCI_REG(SH7751_PCIMCR));
/* NOTE: I'm ignoring the PCI error IRQs for now..
* TODO: add support for the internal error interrupts and
* DMA interrupts...
*/
/* SH7751 init done, set central function init complete */
/* use round robin mode to stop a device starving/overruning */
word = SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN | SH7751_PCICR_ARBM;
outl(word,PCI_REG(SH7751_PCICR));
PCIDBG(2,"PCI: snapgear_pci_init finished\n");
return 1;
}
static inline
uint16_t ata_data(const struct ata_chan *chan)
{
return inw(chan->cmd_bar);
}
static void isicom_tx(unsigned long _data)
{
unsigned long flags, base;
unsigned int retries;
short count = (BOARD_COUNT-1), card;
short txcount, wrd, residue, word_count, cnt;
struct isi_port *port;
struct tty_struct *tty;
card = (prev_card + 1) & 0x0003;
while (count-- > 0) {
if (isi_card[card].status & BOARD_ACTIVE)
break;
card = (card + 1) & 0x0003;
}
if (!(isi_card[card].status & BOARD_ACTIVE))
goto sched_again;
prev_card = card;
count = isi_card[card].port_count;
port = isi_card[card].ports;
base = isi_card[card].base;
spin_lock_irqsave(&isi_card[card].card_lock, flags);
for (retries = 0; retries < 100; retries++) {
if (inw(base + 0xe) & 0x1)
break;
udelay(2);
}
if (retries >= 100)
goto unlock;
tty = tty_port_tty_get(&port->port);
if (tty == NULL)
goto put_unlock;
for (; count > 0; count--, port++) {
if (!(port->port.flags & ASYNC_INITIALIZED) ||
!(port->status & ISI_TXOK))
continue;
txcount = min_t(short, TX_SIZE, port->xmit_cnt);
if (txcount <= 0 || tty->stopped || tty->hw_stopped)
continue;
if (!(inw(base + 0x02) & (1 << port->channel)))
continue;
pr_dbg("txing %d bytes, port%d.\n", txcount,
port->channel + 1);
outw((port->channel << isi_card[card].shift_count) | txcount,
base);
residue = NO;
wrd = 0;
while (1) {
cnt = min_t(int, txcount, (SERIAL_XMIT_SIZE
- port->xmit_tail));
if (residue == YES) {
residue = NO;
if (cnt > 0) {
wrd |= (port->port.xmit_buf[port->xmit_tail]
<< 8);
port->xmit_tail = (port->xmit_tail + 1)
& (SERIAL_XMIT_SIZE - 1);
port->xmit_cnt--;
txcount--;
cnt--;
outw(wrd, base);
} else {
outw(wrd, base);
break;
}
}
if (cnt <= 0)
break;
word_count = cnt >> 1;
outsw(base, port->port.xmit_buf+port->xmit_tail, word_count);
port->xmit_tail = (port->xmit_tail
+ (word_count << 1)) & (SERIAL_XMIT_SIZE - 1);
txcount -= (word_count << 1);
port->xmit_cnt -= (word_count << 1);
if (cnt & 0x0001) {
residue = YES;
wrd = port->port.xmit_buf[port->xmit_tail];
port->xmit_tail = (port->xmit_tail + 1)
& (SERIAL_XMIT_SIZE - 1);
port->xmit_cnt--;
txcount--;
}
}
InterruptTheCard(base);
if (port->xmit_cnt <= 0)
port->status &= ~ISI_TXOK;
if (port->xmit_cnt <= WAKEUP_CHARS)
tty_wakeup(tty);
}
put_unlock:
tty_kref_put(tty);
unlock:
spin_unlock_irqrestore(&isi_card[card].card_lock, flags);
sched_again:
mod_timer(&tx, jiffies + msecs_to_jiffies(10));
}
HPT_U16 os_inw (void *port) { return inw((unsigned)(HPT_UPTR)port); }
/*
* This is the main access entry for i2c-sch access
* adap is i2c_adapter pointer, addr is the i2c device bus address, read_write
* (0 for read and 1 for write), size is i2c transaction type and data is the
* union of transaction for data to be transferred or data read from bus.
* return 0 for success and others for failure.
*/
static s32 sch_access(struct i2c_adapter *adap, u16 addr,
unsigned short flags, char read_write,
u8 command, int size, union i2c_smbus_data *data)
{
int i, len, temp, rc;
/* Make sure the SMBus host is not busy */
temp = inb(SMBHSTSTS) & 0x0f;
if (temp & 0x08) {
dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
return -EAGAIN;
}
temp = inw(SMBHSTCLK);
if (!temp) {
/*
* We can't determine if we have 33 or 25 MHz clock for
* SMBus, so expect 33 MHz and calculate a bus clock of
* 100 kHz. If we actually run at 25 MHz the bus will be
* run ~75 kHz instead which should do no harm.
*/
dev_notice(&sch_adapter.dev,
"Clock divider uninitialized. Setting defaults\n");
outw(backbone_speed / (4 * 100), SMBHSTCLK);
}
dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
(read_write)?"READ":"WRITE");
switch (size) {
case I2C_SMBUS_QUICK:
outb((addr << 1) | read_write, SMBHSTADD);
size = SCH_QUICK;
break;
case I2C_SMBUS_BYTE:
outb((addr << 1) | read_write, SMBHSTADD);
if (read_write == I2C_SMBUS_WRITE)
outb(command, SMBHSTCMD);
size = SCH_BYTE;
break;
case I2C_SMBUS_BYTE_DATA:
outb((addr << 1) | read_write, SMBHSTADD);
outb(command, SMBHSTCMD);
if (read_write == I2C_SMBUS_WRITE)
outb(data->byte, SMBHSTDAT0);
size = SCH_BYTE_DATA;
break;
case I2C_SMBUS_WORD_DATA:
outb((addr << 1) | read_write, SMBHSTADD);
outb(command, SMBHSTCMD);
if (read_write == I2C_SMBUS_WRITE) {
outb(data->word & 0xff, SMBHSTDAT0);
outb((data->word & 0xff00) >> 8, SMBHSTDAT1);
}
size = SCH_WORD_DATA;
break;
case I2C_SMBUS_BLOCK_DATA:
outb((addr << 1) | read_write, SMBHSTADD);
outb(command, SMBHSTCMD);
if (read_write == I2C_SMBUS_WRITE) {
len = data->block[0];
if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
return -EINVAL;
outb(len, SMBHSTDAT0);
for (i = 1; i <= len; i++)
outb(data->block[i], SMBBLKDAT+i-1);
}
size = SCH_BLOCK_DATA;
break;
default:
dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
return -EOPNOTSUPP;
}