void Encoder::end() { int i, j; if(mode == MODE_NOSET) return; detachInterrupt(); io_DisableINT(); mcsif_Disable(mcn, mdn); if(mode == MODE_CAPTURE) { disable_MCINT(mcn, SIFB_CAP1INTBIT); disable_MCINT(mcn, SIFB_CAP2INTBIT); disable_MCINT(mcn, SIFB_CAP3INTBIT); } else { disable_MCINT(mcn, SIFB_TRIGRESETBIT); disable_MCINT(mcn, SIFB_USEREVTBIT); } mode = _mcmode[mcn] = MODE_NOSET; _setZPol = false; io_RestoreINT(); for(i=0; i<4; i++) { if(_encfunc[i] != NULL) break; for(j=0; j<3; j++) if(_pcapfunc[i][j] != NULL) break; } if(i == 4 && j == 3) { mc_outp(MC_GENERAL, 0x38, mc_inp(MC_GENERAL, 0x38) | (1L << mcn)); if(irq_UninstallISR(used_irq, (void*)name) == false) printf("irq_install fail\n"); else used_irq = 0xff; } }
static void write_cmos(unsigned char address, unsigned char buf) { if(address >= EEPROMSIZE_BANK0) // 0~199 return ; pci_dev pcidev; unsigned long int reg; io_DisableINT(); pcidev.bus = 0; pcidev.dev = 7; pcidev.func = 0; reg = pci_dev_read_dw(&pcidev, 0xc0); if(address == 20 || address == 22) //special case { //Set bit 3 to access high 128 bytes RTC SRAM pci_dev_write_dw(&pcidev, 0xc0, reg | 0x00000008); address = (address == 20)? 26:27; outp(0x70, address); } else if(address < 100) // 0~99 low page { //clear bit 3 to access low 128 bytes RTC SRAM pci_dev_write_dw(&pcidev, 0xc0, reg & 0xfffffff7); outp(0x70, address + 28); } else// 100~199 high page { //Set bit 3 to access high 128 bytes RTC SRAM pci_dev_write_dw(&pcidev, 0xc0, reg | 0x00000008); address -= 100; outp(0x70, address + 28); } outp(0x71, buf); // Restore old register value pci_dev_write_dw(&pcidev, 0xc0, reg); io_RestoreINT(); }
DMPAPI(void*) pci_Alloc(unsigned char bus, unsigned char dev, unsigned char fun) { unsigned long tmpid; // just ignore wrong dev & fun :p dev = dev & 0x1f; fun = fun & 0x07; // get VID & DID io_DisableINT(); tmpid = pci_indw(PCI_GET_CF8(bus, dev, fun)); io_RestoreINT(); if (tmpid == 0xffffffffUL) if (fun == 0) { err_print((char*)"%s: invalid PCI device!\n", __FUNCTION__); return NULL; } return alloc_pci(bus, dev, fun); }
static int CAN_ISR(int irq, void *data) { unsigned long isr; CAN_Bus *can = (CAN_Bus *)data; if (((isr = io_In32(can->handle, can->ISR)) & 0x07FFL) != 0x00L) { if (isr & CAN_RXI) { io_DisableINT(); { can->rx_temp.type = (unsigned char)io_In32(can->handle, can->RX.TYPE); can->rx_temp.id = io_In32(can->handle, can->RX.IDR); can->rx_temp.hdata = io_In32(can->handle, can->RX.DATAH); can->rx_temp.ldata = io_In32(can->handle, can->RX.DATAL); PushBufQueue(can->rcvd, (void*)&can->rx_temp); } io_RestoreINT(); io_Out32(can->handle, can->REQ, 0x0100L); // release the received message io_Out32(can->handle, can->ISR, CAN_RXI); } if (isr & CAN_TX0I) { unsigned long stat; stat = io_In32(can->handle, can->TX[0].STAT); if (stat & 0x20L) { can->TX[0].Err_CNT++; can->error = CAN_ERROR_TX0 + (unsigned char)((stat & 0x00070000L) >> 16); if (can->ErrStoreEnable == true) PushQueue(can->err, can->error); if (can->error_handler != NULL) can->error_handler(can); } if ((stat & 0x07L) == 0x05L) can_RoundRobin(can); io_Out32(can->handle, can->ISR, CAN_TX0I); }
DMP_INLINE(void) can_Reset(CAN_Bus *can) // does not reset ID filter table { int i; unsigned long gcr; if (can == NULL) { err_print((char*)"%s: CAN bus is null.\n", __FUNCTION__); return; } if (can->InUse != 1) { err_print((char*)"%s: CAN bus is not in use.\n", __FUNCTION__); return; } /* Software reset */ io_Out32(can->handle, can->GCR, io_In32(can->handle, can->GCR) | 0x01L); // reset CAN registers while (io_In32(can->handle, can->GCR) & 0x01L); can->state = CAN_STAT_ACTIVE; can->error = CAN_ERROR_NONE; can->ArbiLost_CNT = 0; can->Overrun_CNT = 0; can->TEC = 0; can->REC = 0; for (i = 0; i < 3; i++) memset((void*)&can->TX[i], 0, sizeof(can->TX[i])); memset((void*)&can->RX , 0, sizeof(can->RX) ); can_FlushRxQueue((void *)can); can_FlushTxQueue((void *)can); io_DisableINT(); { io_Out32(can->handle, can->IER, CAN_ALL_INT); } io_RestoreINT(); gcr = io_In32(can->handle, can->GCR); if (can->mode & CAN_ID_BYPASS) gcr |= 0x0004000L; if (can->mode & CAN_POWER_SAVING) gcr |= 0x0100000L; io_Out32(can->handle, can->GCR, gcr |= 0x20382L); // Error retry, Arbitration lost retry, Round Robin // Idenfitier filter enable while (io_In32(can->handle, can->GCR) != gcr); }
static int CAN_ISR(int irq, void *data) { unsigned long isr; CAN_Bus *can = (CAN_Bus *)data; if (((isr = io_In32(can->ioHandle, can->ISR)) & 0x07FFL) != 0x00L) { if (isr & CAN_RXI) { unsigned long temp; CANFrame rx_temp; io_DisableINT(); { temp = io_In32(can->ioHandle, can->RX.TYPE); rx_temp.type = (int)(temp & 0x03UL); rx_temp.length = (int)((temp >> 4) & 0x0FUL); rx_temp.identifier = io_In32(can->ioHandle, can->RX.IDR); rx_temp.Data.dword[0] = io_In32(can->ioHandle, can->RX.DATAL); rx_temp.Data.dword[1] = io_In32(can->ioHandle, can->RX.DATAH); PushBufQueue(can->rcvd, (void*)&rx_temp); } io_RestoreINT(); io_Out32(can->ioHandle, can->REQ, 0x0100UL); // release the received message io_Out32(can->ioHandle, can->ISR, CAN_RXI); } if (isr & CAN_TX0I) { unsigned long stat; stat = io_In32(can->ioHandle, can->TX[0].STAT); if (stat & 0x20UL) { can->LastError = CAN_ERROR_TX0 + (unsigned char)((stat & 0x00070000UL) >> 16); if (can->StoreError) PushQueue(can->Error, can->LastError); }
DMPAPI(void) usb_Close(void *vusb) { USB_Device *usb = (USB_Device *)vusb; if (usb == NULL) { err_print((char*)"%s: USB device is null.\n", __FUNCTION__); return; } if (usb->InUse != 0) { io_DisableINT(); { io_outpb(usb->CFR, io_inpb(usb->CFR) & 0xFE); irq_UninstallISR(usb->nIRQ, (void *)usb); } io_RestoreINT(); irq_Close(); io_outpb(usb->CFR, 0x02); // Soft reset while (io_inpb(usb->CFR) & 0x02); #if defined DMP_DOS_DJGPP if (dma_Free(dma_handle) == false) err_print((char*)"%s: Free DMA buffer fail!!\n", __FUNCTION__); #endif ker_Mfree(usb->EP[0].SetupBuf); ker_Mfree(usb->EP[0].InBuf); ker_Mfree(usb->EP[0].OutBuf); ker_Mfree(usb->EP[1].InBuf); ker_Mfree(usb->EP[2].InBuf); ker_Mfree(usb->EP[2].OutBuf); if (io_Close() == false) err_print((char*)"%s: Close IO lib error!!\n", __FUNCTION__); usb->state = USB_DEV_POWERED; usb->InUse = 0; USB_Disconnect(); } DestoryQueue(usb->rcvd); DestoryQueue(usb->xmit); ker_Mfree((void *)usb); }
DMP_INLINE(void) can_RoundRobin(CAN_Bus *can) { if (QueueEmpty(can->xmit)) return; io_DisableINT(); { if (!(io_In32(can->handle, can->REQ) & (0x01L << (round*2)))) { PopBufQueue(can->xmit, (void*)&can->tx_temp); io_Out32(can->handle, can->TX[round].TYPE , (unsigned long)can->tx_temp.type); io_Out32(can->handle, can->TX[round].IDR , can->tx_temp.id); io_Out32(can->handle, can->TX[round].DATAL, can->tx_temp.ldata); io_Out32(can->handle, can->TX[round].DATAH, can->tx_temp.hdata); io_Out32(can->handle, can->REQ, io_In32(can->handle, can->REQ) | (0x01L << (round*2))); round++; if (round == 3) round = 0; } } io_RestoreINT(); }
void Encoder::_ssiInit(unsigned long bits, unsigned long clk, unsigned long wtime, bool gray2bin) { _filterAndSampleWindowInit(mcn, mdn); mcsif_SetMode(mcn, mdn, MCSIF_SSI); if(clk == 0L) clk = 1000000L; // default value if(wtime == 0L) wtime = 20L; // default value if(bits > 32) bits = 32L; // default value clk = ((100000000L)/(clk))/2L; // = ((1/clk)x1000000x100)/2 wtime = wtime * 100L; if(wtime <= clk) return; mcssi_SetClock(mcn, mdn, clk-1L); mcssi_SetWaitTime(mcn, mdn, wtime-1L); mcssi_SetLatchPhase(mcn, mdn, MCSSI_LATCH_PHASE0); mcssi_SetLatchTime(mcn, mdn, 0L); mcssi_SetNumberBITS(mcn, mdn, bits-1L); mcssi_SetCntMode(mcn, mdn, MCSSI_CONTINUE); if(gray2bin == true) mcssi_SetGAY2BINBit(mcn, mdn); #if defined (DMP_DOS_BC) || (DMP_DOS_DJGPP) io_DisableINT(); #elif defined (DMP_LINUX) OSSPINLOCK(encvar); #endif _mcmode[mcn] = MODE_SSI; #if defined (DMP_DOS_BC) || (DMP_DOS_DJGPP) io_RestoreINT(); #elif defined (DMP_LINUX) OSSPINUNLOCK(encvar); #endif }
void Encoder::_pcapInit(void) { _filterAndSampleWindowInit(mcn, mdn); mcsif_SetMode(mcn, mdn, MCSIF_PFAU); mcpfau_SetCapMode1(mcn, mdn, MCPFAU_CAP_BOTH_CLEAR); mcpfau_SetCapInterval1(mcn, mdn, 1L); mcpfau_SetCap1INT(mcn, mdn, 0L); mcpfau_SetPolarity1(mcn, mdn, MCPFAU_POL_NORMAL); mcpfau_SetMask1(mcn, mdn, MCPFAU_MASK_NONE); mcpfau_SetRLDTRIG1(mcn, mdn, MCPFAU_RLDTRIG_DISABLE); mcpfau_SetFAU1TRIG(mcn, mdn, MCPFAU_FAUTRIG_INPUT1); mcpfau_SetFAU1RELS(mcn, mdn, MCPFAU_FAURELS_INPUT0); mcpfau_SetCapMode2(mcn, mdn, MCPFAU_CAP_BOTH_CLEAR); mcpfau_SetCapInterval2(mcn, mdn, 1L); mcpfau_SetCap2INT(mcn, mdn, 0L); mcpfau_SetPolarity2(mcn, mdn, MCPFAU_POL_NORMAL); mcpfau_SetMask2(mcn, mdn, MCPFAU_MASK_NONE); mcpfau_SetRLDTRIG2(mcn, mdn, MCPFAU_RLDTRIG_DISABLE); mcpfau_SetFAU2TRIG(mcn, mdn, MCPFAU_FAUTRIG_INPUT1); mcpfau_SetFAU2RELS(mcn, mdn, MCPFAU_FAURELS_INPUT0); mcpfau_SetCapMode3(mcn, mdn, MCPFAU_CAP_BOTH_CLEAR); mcpfau_SetCapInterval3(mcn, mdn, 1L); mcpfau_SetCap3INT(mcn, mdn, 0L); mcpfau_SetPolarity3(mcn, mdn, MCPFAU_POL_NORMAL); mcpfau_SetMask3(mcn, mdn, MCPFAU_MASK_NONE); mcpfau_SetRLDTRIG3(mcn, mdn, MCPFAU_RLDTRIG_DISABLE); mcpfau_SetFAU3TRIG(mcn, mdn, MCPFAU_FAUTRIG_INPUT1); mcpfau_SetFAU3RELS(mcn, mdn, MCPFAU_FAURELS_INPUT0); io_DisableINT(); _mcmode[mcn] = MODE_CAPTURE; io_RestoreINT(); }
void RTCZero::enableAlarm(uint8_t match) { unsigned char tmp; if(RTCZeroInit == false) return; if(RTCZeroEnable == false) { if(irq_Setting(RTCIRQ, IRQ_EDGE_TRIGGER) == false) { printf("MCM IRQ Setting fail\n"); return; } if(irq_InstallISR(RTCIRQ, rtczero_isr_handler, isrname_rtc) == false) { printf("irq_install fail\n"); return; } } io_DisableINT(); alarmType = match; if(alarmType == ALARMSEC) { outpb_cmos(0x03, inpb_cmos(0x02)); outpb_cmos(0x05, inpb_cmos(0x04)); } else if(alarmType == ALARMMINSEC) { outpb_cmos(0x05, inpb_cmos(0x04)); } tmp = inpb_cmos(0x0B); outpb_cmos(0x0B, tmp | 0x20); // Alarm interrupt io_RestoreINT(); RTCZeroEnable = true; }
static void free_io_base(IO_BASE_t* base) { io_DisableINT(); if (base != NULL) base->iotype = IO_USE_NULLIO; io_RestoreINT(); }
DMP_INLINE(void) outpb_cmos(unsigned char reg, unsigned char data) { io_DisableINT(); io_outpb(0x70, 0x80 | reg); // disable NMI (by setting the 0x80 bit) and assign a RTC register address io_outpb(0x71, data); io_RestoreINT(); }
static unsigned char read_cmos(unsigned char address) { if(address >= EEPROMSIZE_BANK0) // 0~199 return 0; #if (defined(DMP_DOS_BC) || defined(DMP_DOS_DJGPP) || defined(DMP_DOS_WATCOM)) io_DisableINT(); #elif defined (DMP_LINUX) lockCMOS(); #endif void *pciDev = NULL; // south bridge register C0H bit 3 controls CMOS page select unsigned long int reg; unsigned char result; pciDev = pci_Alloc(0x00, 0x07, 0x00); if(pciDev == NULL) { #if (defined(DMP_DOS_BC) || defined(DMP_DOS_DJGPP) || defined(DMP_DOS_WATCOM)) Serial.print("CMOS device doesn't exist\n"); #elif (defined(DMP_LINUX)) printf("CMOS device doesn't exist\n"); #endif return 0; } reg = pci_In32(pciDev, 0xc0); if(address == 20 || address == 22)//special case { //Set bit 3 to access high 128 bytes RTC SRAM pci_Out32(pciDev, 0xc0, reg | 0x00000008); address = (address == 20)? 26:27; io_outpb(0x70, address); } else if(address < 100) // 0~99 low page { //clear bit 3 to access low 128 bytes RTC SRAM pci_Out32(pciDev, 0xc0, reg & 0xfffffff7); io_outpb(0x70, address + 28); } else// 100~199 high page { //Set bit 3 to access high 128 bytes RTC SRAM pci_Out32(pciDev, 0xc0, reg | 0x00000008); address -= 100; io_outpb(0x70, address + 28); } result = io_inpb(0x71); // Restore old register value pci_Out32(pciDev, 0xc0, reg); pci_Free(pciDev); #if (defined(DMP_DOS_BC) || defined(DMP_DOS_DJGPP) || defined(DMP_DOS_WATCOM)) io_RestoreINT(); #elif defined (DMP_LINUX) unLockCMOS(); #endif return result; }
static void mcmsif_close(void) { mcsif_Disable(mc, md); io_DisableINT(); mcm_init[mc] = false; io_RestoreINT(); }
static void free_pci_base(PCI_BASE_t* base) { io_DisableINT(); if (base != NULL) base->addr = 0xffffffffL; io_RestoreINT(); }
DMPAPI(bool) usb_Init(void *vusb) { #if defined DMP_DOS_DJGPP static bool locked = false; int size_temp; #endif USB_Device *usb = (USB_Device *)vusb; if (usb->InUse == 1) return true; // if (USB_IsAttached() == false) return false; USB_Connect(); if (irq_Init() == false) { err_print((char*)"%s: IRQ init fail.\n", __FUNCTION__); io_Close(); return false; } #if defined DMP_DOS_DJGPP if (locked == false) { int i, str_size; DPMI_LOCK_FUNC(SetEPnDLR); DPMI_LOCK_FUNC(Set_Address); DPMI_LOCK_FUNC(Get_Descriptor); DPMI_LOCK_FUNC(Set_Descriptor); DPMI_LOCK_FUNC(Get_Configuration); DPMI_LOCK_FUNC(Set_Configuration); DPMI_LOCK_FUNC(Get_Interface); DPMI_LOCK_FUNC(Set_Interface); DPMI_LOCK_FUNC(Synch_Frame); DPMI_LOCK_FUNC(USB_Standard_Request); DPMI_LOCK_FUNC(Set_Line_Coding); DPMI_LOCK_FUNC(Get_Line_Coding); DPMI_LOCK_FUNC(Set_Control_Line_State); DPMI_LOCK_FUNC(Send_Break); DPMI_LOCK_FUNC(USB_CDC_Request); DPMI_LOCK_FUNC(EP0_SetupHandler); DPMI_LOCK_FUNC(EP0_InHandler); DPMI_LOCK_FUNC(EP0_OutHandler); DPMI_LOCK_FUNC(EP1_InHandler); DPMI_LOCK_FUNC(EP2_InHandler); DPMI_LOCK_FUNC(EP2_OutHandler); DPMI_LOCK_FUNC(usb_Reset); DPMI_LOCK_FUNC(USB_ISR); DPMI_LOCK_VAR(desc_Device); DPMI_LOCK_VAR(desc_Config_Set); DPMI_LOCK_VAR(StringDescTable[0]); DPMI_LOCK_VAR(StringDescTable[1]); DPMI_LOCK_VAR(StringDescTable[2]); DPMI_LOCK_VAR(StringDescTable[3]); DPMI_LOCK_VAR(StringDescTable[4]); DPMI_LOCK_VAR(StringDescTable[5]); DPMI_LOCK_VAR(StringDescTable[6]); locked = true; } #endif io_outpb(usb->CFR, 0x02); // Soft reset while (io_inpb(usb->CFR) & 0x02); if ((usb->EP[0].SetupBuf = (BYTE *)ker_Malloc(sizeof(BYTE)*EP0_MAX_PACKET_SIZE)) == NULL) goto EP0_SETUP_FAIL; if ((usb->EP[0].InBuf = (BYTE *)ker_Malloc(sizeof(BYTE)*EP0_MAX_PACKET_SIZE)) == NULL) goto EP0_IN_FAIL; if ((usb->EP[0].OutBuf = (BYTE *)ker_Malloc(sizeof(BYTE)*EP0_MAX_PACKET_SIZE)) == NULL) goto EP0_OUT_FAIL; if ((usb->EP[1].InBuf = (BYTE *)ker_Malloc(sizeof(BYTE)*EP1_MAX_PACKET_SIZE_IN)) == NULL) goto EP1_IN_FAIL; if ((usb->EP[2].InBuf = (BYTE *)ker_Malloc(sizeof(BYTE)*EP2_MAX_PACKET_SIZE_IN)) == NULL) goto EP2_IN_FAIL; if ((usb->EP[2].OutBuf = (BYTE *)ker_Malloc(sizeof(BYTE)*EP2_MAX_PACKET_SIZE_OUT)) == NULL) goto EP2_OUT_FAIL; #if defined DMP_DOS_DJGPP if ((dma_handle = dma_Alloc(EP0_MAX_PACKET_SIZE + EP0_MAX_PACKET_SIZE + EP0_MAX_PACKET_SIZE + EP1_MAX_PACKET_SIZE_IN + EP2_MAX_PACKET_SIZE_IN + EP2_MAX_PACKET_SIZE_OUT, &dma_addr)) == DMA_FAIL) goto EP2_OUT_FAIL; size_temp = 0; usb->EP[0].SetupPhysical = dma_addr; usb->EP[0].InPhysical = dma_addr + (size_temp += EP0_MAX_PACKET_SIZE); usb->EP[0].OutPhysical = dma_addr + (size_temp += EP0_MAX_PACKET_SIZE); usb->EP[1].InPhysical = dma_addr + (size_temp += EP0_MAX_PACKET_SIZE); usb->EP[2].InPhysical = dma_addr + (size_temp += EP1_MAX_PACKET_SIZE_IN); usb->EP[2].OutPhysical = dma_addr + (size_temp += EP2_MAX_PACKET_SIZE_IN); #else usb->EP[0].SetupPhysical = GrabPhysicalMEM((void *)usb->EP[0].SetupBuf); usb->EP[0].InPhysical = GrabPhysicalMEM((void *)usb->EP[0].InBuf); usb->EP[0].OutPhysical = GrabPhysicalMEM((void *)usb->EP[0].OutBuf); usb->EP[1].InPhysical = GrabPhysicalMEM((void *)usb->EP[1].InBuf); usb->EP[2].InPhysical = GrabPhysicalMEM((void *)usb->EP[2].InBuf); usb->EP[2].OutPhysical = GrabPhysicalMEM((void *)usb->EP[2].OutBuf); #endif // usb->DevAddr = 0x00; // usb->ReadySetAddr = false; // io_outpb(usb->DAR, 0x00); // enable USB device io_outpdw(usb->EP[0].SetupDSR, usb->EP[0].SetupPhysical); io_outpdw(usb->EP[0].InDSR , usb->EP[0].InPhysical); io_outpdw(usb->EP[0].OutDSR , usb->EP[0].OutPhysical); io_outpdw(usb->EP[1].InDSR , usb->EP[1].InPhysical); io_outpdw(usb->EP[2].InDSR , usb->EP[2].InPhysical); io_outpdw(usb->EP[2].OutDSR , usb->EP[2].OutPhysical); io_outpw(usb->EP[0].CtrlTR , 0x2000 | EP0_MAX_PACKET_SIZE); io_outpw(usb->EP[1].InTR , 0x3800 | EP1_MAX_PACKET_SIZE_IN); io_outpw(usb->EP[2].InTR , 0x3000 | EP2_MAX_PACKET_SIZE_IN); io_outpw(usb->EP[2].OutTR , 0x3000 | EP2_MAX_PACKET_SIZE_OUT); SetEPnDLR(usb, EP0, SETUP, ENABLE); // io_outpb(usb->DAR, 0x80); // enable USB device // while (!(io_inpb(usb->DAR) & 0x80)); // ClearQueue(usb->rcvd); // ClearQueue(usb->xmit); // io_DisableINT(); // { // io_outpb(usb->CFR, io_inpb(usb->CFR) & 0xFE); // io_outpdw(usb->IER, ISOF + IBRST + ISUSP + IRESM + SYSERR + // IEP0SETUP + IEP0RX + IEP0TX + IEP1TX + IEP2RX + IEP2TX); // io_outpb(usb->CFR, io_inpb(usb->CFR) | 0x01); // } // io_RestoreINT(); // usb->state = USB_DEV_DEFAULT; io_outpb(usb->DAR, 0x80); // enable USB device while (!(io_inpb(usb->DAR) & 0x80)); io_outpdw(usb->ISR, 0xFFFFFFFFL); io_DisableINT(); { io_outpb(usb->CFR, io_inpb(usb->CFR) & 0xFE); irq_Setting(usb->nIRQ, IRQ_LEVEL_TRIGGER); irq_InstallISR(usb->nIRQ, USB_ISR, (void *)usb); io_outpdw(usb->IER, ISOF + IBRST + ISUSP + IRESM + SYSERR + IEP0SETUP + IEP0RX + IEP0TX + IEP1TX + IEP2RX + IEP2TX); io_outpb(usb->CFR, io_inpb(usb->CFR) | 0x01); } io_RestoreINT(); usb->state = USB_DEV_POWERED; usb->InUse = 1; return true; EP2_OUT_FAIL: ker_Mfree(usb->EP[2].InBuf); EP2_IN_FAIL: ker_Mfree(usb->EP[1].InBuf); EP1_IN_FAIL: ker_Mfree(usb->EP[0].OutBuf); EP0_OUT_FAIL: ker_Mfree(usb->EP[0].InBuf); EP0_IN_FAIL: ker_Mfree(usb->EP[0].SetupBuf); EP0_SETUP_FAIL: err_print((char*)"%s: Alloc endpoint buffers error!!\n", __FUNCTION__); irq_Close(); io_Close(); return false; }
void RTCZero::attachInterrupt(void (*isr)(void)) { io_DisableINT(); isrCallback = isr; io_RestoreINT(); }
void RTCZero::detachInterrupt() { io_DisableINT(); isrCallback = NULL; io_RestoreINT(); }
void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode) { int i; unsigned short crossbar_ioaddr; if(interruptNum >= EXTERNAL_NUM_INTERRUPTS) { printf("This interrupt%d has no one pin to use\n", interruptNum); return; } mc = interruptNum/3; md = MCSIF_MODULEB; if(_userfunc[interruptNum] != NULL) return; if(interrupt_init() == false) return; mcmsif_init(); clear_INTSTATUS(); enable_MCINT(0xfc); // SIFB FAULT INT3/2/1 + STAT3/2/1 = 6 bits crossbar_ioaddr = sb_Read16(0x64)&0xfffe; if (mc == 0) io_outpb(crossbar_ioaddr + 2, 0x01); // GPIO port2: 0A, 0B, 0C, 3A else if (mc == 1) io_outpb(crossbar_ioaddr + 3, 0x02); // GPIO port3: 1A, 1B, 1C, 3B else if(mc == 2) io_outpb(crossbar_ioaddr, 0x03); // GPIO port0: 2A, 2B, 2C, 3C else if(mc == 3) { io_outpb(crossbar_ioaddr + 2, 0x01); io_outpb(crossbar_ioaddr + 3, 0x02); io_outpb(crossbar_ioaddr, 0x03); } mcsif_Disable(mc, md); io_DisableINT(); _userfunc[interruptNum] = userFunc; io_RestoreINT(); switch (mode) { case LOW: sifSetPol[interruptNum%3](mc, md, MCPFAU_POL_INVERSE); sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_INACTIVE); sifSetRelease[interruptNum%3](mc, md, MCPFAU_FAURELS_FSTAT0); sifClearStat[interruptNum%3](mc, md); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_LEVEL0; clear_INTSTATUS(); break; case HIGH: sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_INACTIVE); sifSetRelease[interruptNum%3](mc, md, MCPFAU_FAURELS_FSTAT0); sifClearStat[interruptNum%3](mc, md); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_LEVEL1; clear_INTSTATUS(); break; case CHANGE: sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_BOTH); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_BOTH; break; case FALLING: sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_1TO0); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_1TO0; break; case RISING: sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_0TO1); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_0TO1; break; default: printf("No support this mode\n"); return; } // switch crossbar to MCM_SIF_PIN io_outpb(crossbar_ioaddr + 0x90 + pin_offset[interruptNum], 0x08);//RICH IO mcsif_Enable(mc, md); // If select level-trigger, switch the MASK to "NONE" after sif is enabled. switch (mode) { case LOW: case HIGH: sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_NONE); break; default: break; } }
void attachInterrupt(uint8_t interruptNum, void (*userCallBackFunc)(void), int mode) { unsigned short crossbar_ioaddr; if(interruptNum >= EXTERNAL_NUM_INTERRUPTS) { printf("This interrupt%d has no one pin to use\n", interruptNum); return; } mc = PIN86[INTPINSMAP[interruptNum]].ENCMC; md = PIN86[INTPINSMAP[interruptNum]].ENCMD; if(PIN86[INTPINSMAP[interruptNum]].userfunc != NULL) return; if(interrupt_init() == false) return; mcmsif_init(); clear_INTSTATUS(); enable_MCINT(0xfc); // SIFB FAULT INT3/2/1 + STAT3/2/1 = 6 bits crossbar_ioaddr = sb_Read16(0x64)&0xfffe; mcsif_Disable(mc, md); io_DisableINT(); PIN86[INTPINSMAP[interruptNum]].userfunc = userCallBackFunc; io_RestoreINT(); switch (mode) { case LOW: sifSetPol[interruptNum%3](mc, md, MCPFAU_POL_INVERSE); sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_INACTIVE); sifSetRelease[interruptNum%3](mc, md, MCPFAU_FAURELS_FSTAT0); sifClearStat[interruptNum%3](mc, md); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_LEVEL0; clear_INTSTATUS(); break; case HIGH: sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_INACTIVE); sifSetRelease[interruptNum%3](mc, md, MCPFAU_FAURELS_FSTAT0); sifClearStat[interruptNum%3](mc, md); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_LEVEL1; clear_INTSTATUS(); break; case CHANGE: sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_BOTH); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_BOTH; break; case FALLING: sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_1TO0); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_1TO0; break; case RISING: sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_0TO1); _usedMode[mc][interruptNum%3] = MCPFAU_CAP_0TO1; break; default: printf("No support this mode\n"); return; } // switch crossbar to MCM_SIF_PIN io_outpb(crossbar_ioaddr + 0x90 + PIN86[INTPINSMAP[interruptNum]].gpN, 0x08);//RICH IO mcsif_Enable(mc, md); // If select level-trigger, switch the MASK to "NONE" after sif is enabled. switch (mode) { case LOW: case HIGH: sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_NONE); break; default: break; } }