void c64io_df00_store(WORD addr, BYTE value)
{
DBGRW(("IO: io-df00 w %04x %02x\n", addr, value));
io_store(&c64io_df00_head, addr, value);
}
int exec(Memory entry_p)
{
Instruction insn;
unsigned long clk = 0;
uint32_t cmod;
if(signal(SIGINT, signal_on_sigint) == SIG_ERR) {
err(EXIT_FAILURE, "signal SIGINT");
}
step_by_step = false;
exec_finish = false;
/* initialize internal variable */
memory_is_fault = 0;
memory_io_writeback = 0;
instruction_prefetch_flush();
/* setup system registers */
PSR = 0;
cmod = (PSR & PSR_CMOD_MASK);
PCR = entry_p;
next_PCR = 0xffffffff;
KSPR = (Memory)STACK_DEFAULT;
#if !NO_DEBUG
/* internal debug variable */
traceback_next = 0;
FLAGR.flags = 0x80000000;
prev_FLAGR.flags = 0x80000000;
for(unsigned int i = 0; i < breakp_next; i++) {
NOTICE("Break point[%d]: 0x%08x\n", i, breakp[i]);
}
#endif
NOTICE("Execution Start: entry = 0x%08x\n", PCR);
do {
/* choose stack */
if(cmod != (PSR & PSR_CMOD_MASK)) {
SPR = !cmod ? USPR : KSPR;
}
cmod = (PSR & PSR_CMOD_MASK);
#if !NO_DEBUG
/* break point check */
for(unsigned int i = 0; i < breakp_next; i++) {
if(PCR == breakp[i]) {
step_by_step = true;
break;
}
}
#endif
/* instruction fetch */
insn.value = instruction_fetch(PCR);
if(memory_is_fault) {
/* fault fetch */
DEBUGINT("[FAULT] Instruction fetch: %08x\n", PCR);
goto fault;
}
#if !NO_DEBUG
if(DEBUG || step_by_step) {
puts("---");
print_instruction(insn);
}
#endif
/* execution */
insn_dispatch(insn);
fault:
if(memory_is_fault) {
/* faulting memory access */
interrupt_dispatch_nonmask(memory_is_fault);
next_PCR = PCR;
memory_io_writeback = 0;
memory_is_fault = 0;
}
else if(memory_io_writeback) {
/* sync io */
io_store(memory_io_writeback);
memory_io_writeback = 0;
}
/* writeback SP */
if(cmod) {
USPR = SPR;
}
else {
KSPR = SPR;
}
#if !NO_DEBUG
if(step_by_step) {
step_by_step_pause();
}
else {
if(DEBUG && DEBUG_REG) { print_registers(); }
if(DEBUG_TRACE) { print_traceback(); }
if(DEBUG_STACK) { print_stack(SPR); }
if(DEBUG_DPS) { dps_info(); }
}
#endif
if(!(clk & MONITOR_RECV_INTERVAL_MASK)) {
if((PSR & PSR_IM_ENABLE) && IDT_ISENABLE(IDT_DPS_LS_NUM)) {
dps_sci_recv();
}
if(MONITOR) {
monitor_method_recv();
monitor_send_queue();
}
}
/* next */
if(next_PCR != 0xffffffff) {
#if !NO_DEBUG
/* alignment check */
if(next_PCR & 0x3) {
abort_sim();
errx(EXIT_FAILURE, "invalid branch addres. %08x", next_PCR);
}
#endif
PCR = next_PCR;
next_PCR = 0xffffffff;
}
else {
PCR += 4;
}
/* interrupt check */
interrupt_dispatcher();
#if !NO_DEBUG
/* for invalid flags checking */
prev_FLAGR.flags = FLAGR.flags;
FLAGR._invalid |= 1;
#endif
/* next cycle */
clk++;
} while(!(PCR == 0 && GR[31] == 0 && DEBUG_EXIT_B0) && !exec_finish);
/* DEBUG_EXIT_B0: exit if b rret && rret == 0 */
NOTICE("---- Program Terminated ----\n");
print_instruction(insn);
print_registers();
return 0;
}
void vic20io3_store(WORD addr, BYTE value)
{
DBGRW(("IO: io3 w %04x %02x\n", addr, value));
io_store(&vic20io3_head, addr, value);
}
