static inline void clear_ioasic_irq(unsigned int irq) { u32 sir; sir = ~(1 << (irq - ioasic_irq_base)); ioasic_write(IO_REG_SIR, sir); }
static inline void mask_ioasic_irq(unsigned int irq) { u32 simr; simr = ioasic_read(IO_REG_SIMR); simr &= ~(1 << (irq - ioasic_irq_base)); ioasic_write(IO_REG_SIMR, simr); }
static inline void unmask_ioasic_irq(unsigned int irq) { u32 simr; simr = ioasic_read(SIMR); simr |= (1 << (irq - ioasic_irq_base)); ioasic_write(SIMR, simr); }
static void mask_ioasic_irq(struct irq_data *d) { u32 simr; simr = ioasic_read(IO_REG_SIMR); simr &= ~(1 << (d->irq - ioasic_irq_base)); ioasic_write(IO_REG_SIMR, simr); }
void __init init_ioasic_irqs(int base) { int i; /* Mask interrupts. */ ioasic_write(IO_REG_SIMR, 0); fast_iob(); for (i = base; i < base + IO_INR_DMA; i++) set_irq_chip_and_handler(i, &ioasic_irq_type, handle_level_irq); for (; i < base + IO_IRQ_LINES; i++) set_irq_chip(i, &ioasic_dma_irq_type); ioasic_irq_base = base; }
void __init init_ioasic_irqs(int base) { int i; /* Mask interrupts. */ ioasic_write(SIMR, 0); for (i = base; i < base + IO_INR_DMA; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = 0; irq_desc[i].depth = 1; irq_desc[i].handler = &ioasic_irq_type; } for (; i < base + IO_IRQ_LINES; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = 0; irq_desc[i].depth = 1; irq_desc[i].handler = &ioasic_dma_irq_type; } ioasic_irq_base = base; }
static void dec_ioasic_hpt_init(unsigned int count) { ioasic_write(IO_REG_FCTR, ioasic_read(IO_REG_FCTR) - count); }