/** * memremap() - remap an iomem_resource as cacheable memory * @offset: iomem resource start address * @size: size of remap * @flags: any of MEMREMAP_WB, MEMREMAP_WT and MEMREMAP_WC * * memremap() is "ioremap" for cases where it is known that the resource * being mapped does not have i/o side effects and the __iomem * annotation is not applicable. In the case of multiple flags, the different * mapping types will be attempted in the order listed below until one of * them succeeds. * * MEMREMAP_WB - matches the default mapping for System RAM on * the architecture. This is usually a read-allocate write-back cache. * Morever, if MEMREMAP_WB is specified and the requested remap region is RAM * memremap() will bypass establishing a new mapping and instead return * a pointer into the direct map. * * MEMREMAP_WT - establish a mapping whereby writes either bypass the * cache or are written through to memory and never exist in a * cache-dirty state with respect to program visibility. Attempts to * map System RAM with this mapping type will fail. * * MEMREMAP_WC - establish a writecombine mapping, whereby writes may * be coalesced together (e.g. in the CPU's write buffers), but is otherwise * uncached. Attempts to map System RAM with this mapping type will fail. */ void *memremap(resource_size_t offset, size_t size, unsigned long flags) { int is_ram = region_intersects(offset, size, IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE); void *addr = NULL; if (!flags) return NULL; if (is_ram == REGION_MIXED) { WARN_ONCE(1, "memremap attempted on mixed range %pa size: %#lx\n", &offset, (unsigned long) size); return NULL; } /* Try all mapping types requested until one returns non-NULL */ if (flags & MEMREMAP_WB) { /* * MEMREMAP_WB is special in that it can be satisifed * from the direct map. Some archs depend on the * capability of memremap() to autodetect cases where * the requested range is potentially in System RAM. */ if (is_ram == REGION_INTERSECTS) addr = try_ram_remap(offset, size); if (!addr) addr = arch_memremap_wb(offset, size); } /* * If we don't have a mapping yet and other request flags are * present then we will be attempting to establish a new virtual * address mapping. Enforce that this mapping is not aliasing * System RAM. */ if (!addr && is_ram == REGION_INTERSECTS && flags != MEMREMAP_WB) { WARN_ONCE(1, "memremap attempted on ram %pa size: %#lx\n", &offset, (unsigned long) size); return NULL; } if (!addr && (flags & MEMREMAP_WT)) addr = ioremap_wt(offset, size); if (!addr && (flags & MEMREMAP_WC)) addr = ioremap_wc(offset, size); return addr; }
/** * memremap() - remap an iomem_resource as cacheable memory * @offset: iomem resource start address * @size: size of remap * @flags: either MEMREMAP_WB or MEMREMAP_WT * * memremap() is "ioremap" for cases where it is known that the resource * being mapped does not have i/o side effects and the __iomem * annotation is not applicable. * * MEMREMAP_WB - matches the default mapping for "System RAM" on * the architecture. This is usually a read-allocate write-back cache. * Morever, if MEMREMAP_WB is specified and the requested remap region is RAM * memremap() will bypass establishing a new mapping and instead return * a pointer into the direct map. * * MEMREMAP_WT - establish a mapping whereby writes either bypass the * cache or are written through to memory and never exist in a * cache-dirty state with respect to program visibility. Attempts to * map "System RAM" with this mapping type will fail. */ void *memremap(resource_size_t offset, size_t size, unsigned long flags) { int is_ram = region_intersects(offset, size, "System RAM"); void *addr = NULL; if (is_ram == REGION_MIXED) { WARN_ONCE(1, "memremap attempted on mixed range %pa size: %#lx\n", &offset, (unsigned long) size); return NULL; } /* Try all mapping types requested until one returns non-NULL */ if (flags & MEMREMAP_WB) { flags &= ~MEMREMAP_WB; /* * MEMREMAP_WB is special in that it can be satisifed * from the direct map. Some archs depend on the * capability of memremap() to autodetect cases where * the requested range is potentially in "System RAM" */ if (is_ram == REGION_INTERSECTS) addr = __va(offset); else addr = ioremap_cache(offset, size); } /* * If we don't have a mapping yet and more request flags are * pending then we will be attempting to establish a new virtual * address mapping. Enforce that this mapping is not aliasing * "System RAM" */ if (!addr && is_ram == REGION_INTERSECTS && flags) { WARN_ONCE(1, "memremap attempted on ram %pa size: %#lx\n", &offset, (unsigned long) size); return NULL; } if (!addr && (flags & MEMREMAP_WT)) { flags &= ~MEMREMAP_WT; addr = ioremap_wt(offset, size); } return addr; }
static struct pmem_device *pmem_alloc(struct device *dev, struct resource *res) { struct pmem_device *pmem; struct gendisk *disk; int idx, err; err = -ENOMEM; pmem = kzalloc(sizeof(*pmem), GFP_KERNEL); if (!pmem) goto out; pmem->phys_addr = res->start; pmem->size = resource_size(res); err = -EINVAL; if (!request_mem_region(pmem->phys_addr, pmem->size, "pmem")) { dev_warn(dev, "could not reserve region [0x%pa:0x%zx]\n", &pmem->phys_addr, pmem->size); goto out_free_dev; } /* * Map the memory as write-through, as we can't write back the contents * of the CPU caches in case of a crash. */ err = -ENOMEM; pmem->virt_addr = ioremap_wt(pmem->phys_addr, pmem->size); if (!pmem->virt_addr) goto out_release_region; pmem->pmem_queue = blk_alloc_queue(GFP_KERNEL); if (!pmem->pmem_queue) goto out_unmap; blk_queue_make_request(pmem->pmem_queue, pmem_make_request); blk_queue_max_hw_sectors(pmem->pmem_queue, 1024); blk_queue_bounce_limit(pmem->pmem_queue, BLK_BOUNCE_ANY); disk = alloc_disk(PMEM_MINORS); if (!disk) goto out_free_queue; idx = atomic_inc_return(&pmem_index) - 1; disk->major = pmem_major; disk->first_minor = PMEM_MINORS * idx; disk->fops = &pmem_fops; disk->private_data = pmem; disk->queue = pmem->pmem_queue; disk->flags = GENHD_FL_EXT_DEVT; sprintf(disk->disk_name, "pmem%d", idx); disk->driverfs_dev = dev; set_capacity(disk, pmem->size >> 9); pmem->pmem_disk = disk; add_disk(disk); return pmem; out_free_queue: blk_cleanup_queue(pmem->pmem_queue); out_unmap: iounmap(pmem->virt_addr); out_release_region: release_mem_region(pmem->phys_addr, pmem->size); out_free_dev: kfree(pmem); out: return ERR_PTR(err); }
static int hpfb_init_one(unsigned long phys_base, unsigned long virt_base) { unsigned long fboff, fb_width, fb_height, fb_start; int ret; fb_regs = virt_base; fboff = (in_8(fb_regs + HPFB_FBOMSB) << 8) | in_8(fb_regs + HPFB_FBOLSB); fb_info.fix.smem_start = (in_8(fb_regs + fboff) << 16); if (phys_base >= DIOII_BASE) { fb_info.fix.smem_start += phys_base; } if (DIO_SECID(fb_regs) != DIO_ID2_TOPCAT) { /* This is the magic incantation the HP X server uses to make Catseye boards work. */ while (in_be16(fb_regs+0x4800) & 1) ; out_be16(fb_regs+0x4800, 0); /* Catseye status */ out_be16(fb_regs+0x4510, 0); /* VB */ out_be16(fb_regs+0x4512, 0); /* TCNTRL */ out_be16(fb_regs+0x4514, 0); /* ACNTRL */ out_be16(fb_regs+0x4516, 0); /* PNCNTRL */ out_be16(fb_regs+0x4206, 0x90); /* RUG Command/Status */ out_be16(fb_regs+0x60a2, 0); /* Overlay Mask */ out_be16(fb_regs+0x60bc, 0); /* Ram Select */ } /* * Fill in the available video resolution */ fb_width = (in_8(fb_regs + HPFB_FBWMSB) << 8) | in_8(fb_regs + HPFB_FBWLSB); fb_info.fix.line_length = fb_width; fb_height = (in_8(fb_regs + HPFB_FBHMSB) << 8) | in_8(fb_regs + HPFB_FBHLSB); fb_info.fix.smem_len = fb_width * fb_height; fb_start = (unsigned long)ioremap_wt(fb_info.fix.smem_start, fb_info.fix.smem_len); hpfb_defined.xres = (in_8(fb_regs + HPFB_DWMSB) << 8) | in_8(fb_regs + HPFB_DWLSB); hpfb_defined.yres = (in_8(fb_regs + HPFB_DHMSB) << 8) | in_8(fb_regs + HPFB_DHLSB); hpfb_defined.xres_virtual = hpfb_defined.xres; hpfb_defined.yres_virtual = hpfb_defined.yres; hpfb_defined.bits_per_pixel = in_8(fb_regs + HPFB_NUMPLANES); printk(KERN_INFO "hpfb: framebuffer at 0x%lx, mapped to 0x%lx, size %dk\n", fb_info.fix.smem_start, fb_start, fb_info.fix.smem_len/1024); printk(KERN_INFO "hpfb: mode is %dx%dx%d, linelength=%d\n", hpfb_defined.xres, hpfb_defined.yres, hpfb_defined.bits_per_pixel, fb_info.fix.line_length); /* * Give the hardware a bit of a prod and work out how many bits per * pixel are supported. */ out_8(fb_regs + TC_WEN, 0xff); out_8(fb_regs + TC_PRR, RR_COPY); out_8(fb_regs + TC_FBEN, 0xff); out_8(fb_start, 0xff); fb_bitmask = in_8(fb_start); out_8(fb_start, 0); /* * Enable reading/writing of all the planes. */ out_8(fb_regs + TC_WEN, fb_bitmask); out_8(fb_regs + TC_PRR, RR_COPY); out_8(fb_regs + TC_REN, fb_bitmask); out_8(fb_regs + TC_FBEN, fb_bitmask); /* * Clear the screen. */ topcat_blit(0, 0, 0, 0, fb_width, fb_height, RR_CLEAR); /* * Let there be consoles.. */ if (DIO_SECID(fb_regs) == DIO_ID2_TOPCAT) strcat(fb_info.fix.id, "Topcat"); else strcat(fb_info.fix.id, "Catseye"); fb_info.fbops = &hpfb_ops; fb_info.flags = FBINFO_DEFAULT; fb_info.var = hpfb_defined; fb_info.screen_base = (char *)fb_start; ret = fb_alloc_cmap(&fb_info.cmap, 1 << hpfb_defined.bits_per_pixel, 0); if (ret < 0) goto unmap_screen_base; ret = register_framebuffer(&fb_info); if (ret < 0) goto dealloc_cmap; fb_info(&fb_info, "%s frame buffer device\n", fb_info.fix.id); return 0; dealloc_cmap: fb_dealloc_cmap(&fb_info.cmap); unmap_screen_base: if (fb_info.screen_base) { iounmap(fb_info.screen_base); fb_info.screen_base = NULL; } return ret; }