static int uv_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { struct uv_irq_2_mmr_pnode *chip_data; struct irq_alloc_info *info = arg; struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq); int ret; if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_UV) return -EINVAL; chip_data = kmalloc_node(sizeof(*chip_data), GFP_KERNEL, irq_data_get_node(irq_data)); if (!chip_data) return -ENOMEM; ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); if (ret >= 0) { if (info->uv_limit == UV_AFFINITY_CPU) irq_set_status_flags(virq, IRQ_NO_BALANCING); else irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); chip_data->pnode = uv_blade_to_pnode(info->uv_blade); chip_data->offset = info->uv_offset; irq_domain_set_info(domain, virq, virq, &uv_irq_chip, chip_data, handle_percpu_irq, NULL, info->uv_name); } else { kfree(chip_data); } return ret; }
static void htirq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq); BUG_ON(nr_irqs != 1); kfree(irq_data->chip_data); irq_domain_free_irqs_top(domain, virq, nr_irqs); }
static void gicv2m_irq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { struct irq_data *d = irq_domain_get_irq_data(domain, virq); struct v2m_data *v2m = irq_data_get_irq_chip_data(d); BUG_ON(nr_irqs != 1); gicv2m_unalloc_msi(v2m, d->hwirq); irq_domain_free_irqs_parent(domain, virq, nr_irqs); }
static void uv_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq); BUG_ON(nr_irqs != 1); kfree(irq_data->chip_data); irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT); irq_clear_status_flags(virq, IRQ_NO_BALANCING); irq_domain_free_irqs_top(domain, virq, nr_irqs); }
static void xgene_gpio_sb_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { struct irq_data *d; unsigned int i; for (i = 0; i < nr_irqs; i++) { d = irq_domain_get_irq_data(domain, virq + i); irq_domain_reset_irq_data(d); } }
/** * crossbar_domain_free - unmap/free a crossbar<->irq connection * @domain: domain of irq to unmap * @virq: virq number * @nr_irqs: number of irqs to free * * We do not maintain a use count of total number of map/unmap * calls for a particular irq to find out if a irq can be really * unmapped. This is because unmap is called during irq_dispose_mapping(irq), * after which irq is anyways unusable. So an explicit map has to be called * after that. */ static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { int i; raw_spin_lock(&cb->lock); for (i = 0; i < nr_irqs; i++) { struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); irq_domain_reset_irq_data(d); cb->irq_map[d->hwirq] = IRQ_FREE; cb->write(d->hwirq, cb->safe_map); } raw_spin_unlock(&cb->lock); }
static int hyperv_irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { struct irq_alloc_info *info = arg; struct irq_data *irq_data; struct irq_desc *desc; int ret = 0; if (!info || info->type != X86_IRQ_ALLOC_TYPE_IOAPIC || nr_irqs > 1) return -EINVAL; ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); if (ret < 0) return ret; irq_data = irq_domain_get_irq_data(domain, virq); if (!irq_data) { irq_domain_free_irqs_common(domain, virq, nr_irqs); return -EINVAL; } irq_data->chip = &hyperv_ir_chip; /* * If there is interrupt remapping function of IOMMU, setting irq * affinity only needs to change IRTE of IOMMU. But Hyper-V doesn't * support interrupt remapping function, setting irq affinity of IO-APIC * interrupts still needs to change IO-APIC registers. But ioapic_ * configure_entry() will ignore value of cfg->vector and cfg-> * dest_apicid when IO-APIC's parent irq domain is not the vector * domain.(See ioapic_configure_entry()) In order to setting vector * and dest_apicid to IO-APIC register, IO-APIC entry pointer is saved * in the chip_data and hyperv_irq_remapping_activate()/hyperv_ir_set_ * affinity() set vector and dest_apicid directly into IO-APIC entry. */ irq_data->chip_data = info->ioapic_entry; /* * Hypver-V IO APIC irq affinity should be in the scope of * ioapic_max_cpumask because no irq remapping support. */ desc = irq_data_to_desc(irq_data); cpumask_copy(desc->irq_common_data.affinity, &ioapic_max_cpumask); return 0; }
static void gicp_irq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { struct mvebu_gicp *gicp = domain->host_data; struct irq_data *d = irq_domain_get_irq_data(domain, virq); if (d->hwirq >= gicp->spi_cnt) { dev_err(gicp->dev, "Invalid hwirq %lu\n", d->hwirq); return; } irq_domain_free_irqs_parent(domain, virq, nr_irqs); spin_lock(&gicp->spi_lock); __clear_bit(d->hwirq, gicp->spi_bitmap); spin_unlock(&gicp->spi_lock); }
static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq) { struct of_phandle_args args; struct irq_data *d; int err; args.np = domain->parent->of_node; args.args_count = 3; args.args[0] = 0; args.args[1] = hwirq - 32; args.args[2] = IRQ_TYPE_EDGE_RISING; err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args); if (err) return err; /* Configure the interrupt line to be edge */ d = irq_domain_get_irq_data(domain->parent, virq); d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING); return 0; }