static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
{
switch (type) {
case IRQ_TYPE_EDGE_RISING:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */
irq_set_handler(d->irq, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */
irq_set_handler(d->irq, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */
irq_set_handler(d->irq, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */
irq_set_handler(d->irq, handle_level_irq);
break;
/* IRQ_TYPE_EDGE_BOTH is not supported */
default:
printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
return -1;
}
return 0;
}
void __init gemini_init_irq(void)
{
unsigned int i, mode = 0, level = 0;
/*
* Disable the idle handler by default since it is buggy
* For more info see arch/arm/mach-gemini/idle.c
*/
disable_hlt();
request_resource(&iomem_resource, &irq_resource);
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip(i, &gemini_irq_chip);
if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
irq_set_handler(i, handle_edge_irq);
mode |= 1 << i;
level |= 1 << i;
} else {
irq_set_handler(i, handle_level_irq);
}
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* Disable all interrupts */
__raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
__raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
/* Set interrupt mode */
__raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
__raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
}
void __init gemini_init_irq(void)
{
unsigned int i, mode = 0, level = 0;
/*
*/
disable_hlt();
request_resource(&iomem_resource, &irq_resource);
for (i = 0; i < NR_IRQS; i++) {
irq_set_chip(i, &gemini_irq_chip);
if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
irq_set_handler(i, handle_edge_irq);
mode |= 1 << i;
level |= 1 << i;
} else {
irq_set_handler(i, handle_level_irq);
}
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* */
__raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
__raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
/* */
__raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
__raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE)));
}
static int sprd_irq_set_type(struct irq_data *data, unsigned int flow_type)
{
/* TODO: make sure our INTCV really has nothing to do with type/polarity */
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
irq_set_handler(data->irq, handle_edge_irq);
}
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
irq_set_handler(data->irq, handle_level_irq);
}
return 0;
}
void __init init_IRQ(void)
{
unsigned int irq;
request_resource(&iomem_resource, &irq_resource);
/* disable all IRQs */
writel(0, INTC_ICMR);
/* all IRQs are IRQ, not REAL */
writel(0, INTC_ICLR);
/* clear all GPIO edge detects */
writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR);
writel(0, GPIO_GFER);
writel(0, GPIO_GRER);
writel(0x0FFFFFFF, GPIO_GEDR);
writel(1, INTC_ICCR);
for (irq = 0; irq < IRQ_GPIOHIGH; irq++) {
irq_set_chip(irq, &puv3_low_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
irq_modify_status(irq,
IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
0);
}
for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) {
irq_set_chip(irq, &puv3_normal_chip);
irq_set_handler(irq, handle_level_irq);
irq_modify_status(irq,
IRQ_NOREQUEST | IRQ_NOAUTOEN,
IRQ_NOPROBE);
}
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) {
irq_set_chip(irq, &puv3_high_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
irq_modify_status(irq,
IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
0);
}
/*
* Install handler for GPIO 0-27 edge detect interrupts
*/
irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);
#ifdef CONFIG_PUV3_GPIO
puv3_init_gpio();
#endif
}
void InstallDefaultCrashHandler()
{
#if defined ION_PLATFORM_WINDOWS
SetUnhandledExceptionFilter(Win32CrashHandler);
#elif defined ION_PLATFORM_DREAMCAST
assert_set_handler(DreamcastAssertHandler);
irq_set_handler(EXC_ILLEGAL_INSTR, DreamcastExceptionHandler);
irq_set_handler(EXC_SLOT_ILLEGAL_INSTR, DreamcastExceptionHandler);
irq_set_handler(EXC_DATA_ADDRESS_READ, DreamcastExceptionHandler);
irq_set_handler(EXC_DATA_ADDRESS_WRITE, DreamcastExceptionHandler);
irq_set_handler(EXC_USER_BREAK_PRE, DreamcastExceptionHandler);
#endif
}
static void claim_cpu_irqs(void)
{
int i;
for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
irq_set_chip_and_handler(i, &cpu_interrupt_type,
handle_percpu_irq);
}
irq_set_handler(TIMER_IRQ, handle_percpu_irq);
setup_irq(TIMER_IRQ, &timer_action);
#ifdef CONFIG_SMP
irq_set_handler(IPI_IRQ, handle_percpu_irq);
setup_irq(IPI_IRQ, &ipi_action);
#endif
}
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned int ebit, irq = d->irq;
u16 pa, tb;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
tb = 0x1;
break;
case IRQ_TYPE_EDGE_FALLING:
tb = 0x2;
break;
case IRQ_TYPE_EDGE_BOTH:
tb = 0x3;
break;
default:
/* Level triggered */
tb = 0;
break;
}
if (tb)
irq_set_handler(irq, handle_edge_irq);
ebit = irq2ebit(irq) * 2;
pa = __raw_readw(MCFEPORT_EPPAR);
pa = (pa & ~(0x3 << ebit)) | (tb << ebit);
__raw_writew(pa, MCFEPORT_EPPAR);
return 0;
}
/*
* This function should be called during kernel startup to initialize
* the machine vector table.
*/
void __init init_IRQ(void)
{
int i;
/* set up the vectors */
for (i = 72; i < 256; ++i)
_ramvec[i] = (e_vector) bad_interrupt;
_ramvec[32] = system_call;
_ramvec[65] = (e_vector) inthandler1;
_ramvec[66] = (e_vector) inthandler2;
_ramvec[67] = (e_vector) inthandler3;
_ramvec[68] = (e_vector) inthandler4;
_ramvec[69] = (e_vector) inthandler5;
_ramvec[70] = (e_vector) inthandler6;
_ramvec[71] = (e_vector) inthandler7;
IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */
/* turn off all interrupts */
IMR = ~0;
for (i = 0; (i < NR_IRQS); i++) {
irq_set_chip(i, &intc_irq_chip);
irq_set_handler(i, handle_level_irq);
}
}
/**
* irq_sim_init - Initialize the interrupt simulator: allocate a range of
* dummy interrupts.
*
* @sim: The interrupt simulator object to initialize.
* @num_irqs: Number of interrupts to allocate
*
* Returns 0 on success and a negative error number on failure.
*/
int irq_sim_init(struct irq_sim *sim, unsigned int num_irqs)
{
int i;
sim->irqs = kmalloc_array(num_irqs, sizeof(*sim->irqs), GFP_KERNEL);
if (!sim->irqs)
return -ENOMEM;
sim->irq_base = irq_alloc_descs(-1, 0, num_irqs, 0);
if (sim->irq_base < 0) {
kfree(sim->irqs);
return sim->irq_base;
}
for (i = 0; i < num_irqs; i++) {
sim->irqs[i].irqnum = sim->irq_base + i;
sim->irqs[i].enabled = false;
irq_set_chip(sim->irq_base + i, &irq_sim_irqchip);
irq_set_chip_data(sim->irq_base + i, &sim->irqs[i]);
irq_set_handler(sim->irq_base + i, &handle_simple_irq);
irq_modify_status(sim->irq_base + i,
IRQ_NOREQUEST | IRQ_NOAUTOEN, IRQ_NOPROBE);
}
init_irq_work(&sim->work_ctx.work, irq_sim_handle_irq);
sim->irq_count = num_irqs;
return 0;
}
void __init tcc8k_init_irq(void)
{
int irqno;
/* Mask and clear all interrupts */
PIC0_IEN = 0x00000000;
PIC0_CREQ = 0xffffffff;
PIC1_IEN = 0x00000000;
PIC1_CREQ = 0xffffffff;
PIC0_MEN0 = 0x00000003;
PIC1_MEN1 = 0x00000003;
PIC1_MEN = 0x00000003;
/* let all IRQs be level triggered */
PIC0_TMODE = 0xffffffff;
PIC1_TMODE = 0xffffffff;
/* all IRQs are IRQs (not FIQs) */
PIC0_IRQSEL = 0xffffffff;
PIC1_IRQSEL = 0xffffffff;
for (irqno = 0; irqno < NR_IRQS; irqno++) {
if (irqno < 32)
irq_set_chip(irqno, &tcc8000_irq_chip0);
else
irq_set_chip(irqno, &tcc8000_irq_chip1);
irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
static int cs75xx_gpio_remove(struct platform_device *pdev)
{
int i, j;
gpio_dbgmsg("Function: %s\n", __func__);
/* disable irq and deregister to gpiolib */
for (i = 0; i < GPIO_BANK_NUM; i++) {
/* disable, unmask and clear all interrupts */
__raw_writel(0x0, cs75xx_gpio_base[i] + CS75XX_GPIO_IE);
__raw_writel(~0x0, cs75xx_gpio_base[i] + CS75XX_GPIO_INT);
for (j = GPIO_IRQ_BASE + i * GPIO_BANK_SIZE;
j < GPIO_IRQ_BASE + (i + 1) * GPIO_BANK_SIZE; j++) {
irq_set_chip(j, NULL);
irq_set_handler(j, NULL);
set_irq_flags(j, 0);
}
irq_set_chained_handler(cs75xx_irq_gpio[i], NULL);
irq_set_handler_data(cs75xx_irq_gpio[i], NULL);
}
BUG_ON(gpiochip_remove(&cs75xx_gpio_chip));
for (i = 0; i < GPIO_BANK_NUM; i++)
__raw_writel(0x0, cs75xx_global_base + CS75XX_GPIO_MUX_0 + i*4); // disable valid gpio pin
return 0;
}
static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
unsigned int irq = d->irq;
u16 pa, tb;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
tb = 0x1;
break;
case IRQ_TYPE_EDGE_FALLING:
tb = 0x2;
break;
case IRQ_TYPE_EDGE_BOTH:
tb = 0x3;
break;
default:
tb = 0;
break;
}
if (tb)
irq_set_handler(irq, handle_edge_irq);
irq -= EINT0;
pa = __raw_readw(MCFEPORT_EPPAR);
pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2));
__raw_writew(pa, MCFEPORT_EPPAR);
return 0;
}
/* ARM Interrupt Controller Initialization */
void __init m2_init_irq(void)
{
unsigned int irq;
/* Disable all interrupt requests */
WRITE_CBUS_REG(A9_0_IRQ_IN0_INTR_MASK, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_MASK, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN3_INTR_MASK, 0);
/* Clear all interrupts */
WRITE_CBUS_REG(A9_0_IRQ_IN0_INTR_STAT_CLR, ~0);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_STAT_CLR, ~0);
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_STAT_CLR, ~0);
WRITE_CBUS_REG(A9_0_IRQ_IN3_INTR_STAT_CLR, ~0);
/* Set all interrupts to IRQ */
WRITE_CBUS_REG(A9_0_IRQ_IN0_INTR_FIRQ_SEL, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN1_INTR_FIRQ_SEL, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_FIRQ_SEL, 0);
WRITE_CBUS_REG(A9_0_IRQ_IN3_INTR_FIRQ_SEL, 0);
/* set up genirq dispatch */
for (irq = 0; irq < NR_IRQS; irq++) {
irq_set_chip(irq, &m2_irq_chip);
irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}
static struct mcuio_soft_hc *__setup_shc(const struct mcuio_soft_hc_ops *ops,
void *priv)
{
struct mcuio_soft_hc *shc = kzalloc(sizeof(*shc), GFP_KERNEL);
if (!shc)
return ERR_PTR(-ENOMEM);
init_kthread_worker(&shc->irq_kworker);
shc->irq_kworker_task = kthread_run(kthread_worker_fn,
&shc->irq_kworker,
"shc_irq");
if (IS_ERR(shc->irq_kworker_task)) {
pr_err("failed to create irq tsk for shc\n");
return ERR_PTR(PTR_ERR(shc->irq_kworker_task));
}
init_kthread_work(&shc->do_irq, __do_irq);
shc->ops = ops;
shc->priv = priv;
shc->rx_circ_buf.head = shc->rx_circ_buf.tail = 0;
shc->rx_circ_buf.buf = shc->rx_buf;
shc->chip.name = "MCUIO-SHC";
shc->chip.irq_mask = mcuio_soft_hc_irq_mask;
shc->chip.irq_unmask = mcuio_soft_hc_irq_unmask;
shc->irqno = irq_alloc_desc(0);
irq_set_chip(shc->irqno, &shc->chip);
irq_set_handler(shc->irqno, &handle_simple_irq);
irq_modify_status(shc->irqno,
IRQ_NOREQUEST | IRQ_NOAUTOEN,
IRQ_NOPROBE);
return shc;
}
static int pod_gpio_remove(struct platform_device *pdev)
{
struct resource *resource_memory, *resource_irq;
struct pod_gpio_chip *cg_chip = dev_get_drvdata(&pdev->dev);
unsigned int irq;
/* Remove the GPIO chip */
if (gpiochip_remove(&cg_chip->chip))
dev_err(&pdev->dev, "gpio_chip remove failed\n");
if (cg_chip->reg_base)
iounmap(cg_chip->reg_base);
kfree(cg_chip);
resource_memory = platform_get_resource(pdev, IORESOURCE_MEM, 0);
resource_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
release_mem_region(resource_memory->start,
resource_size(resource_memory));
for (irq = IRQ_GPIO_POD(0) ; irq < IRQ_GPIO_POD(16) ; irq++) {
irq_set_chip(irq, NULL);
irq_set_handler(irq, NULL);
set_irq_flags(irq, 0);
}
free_irq(resource_irq->start, cg_chip);
dev_set_drvdata(&pdev->dev, NULL);
return 0;
}
static void __init msm8x60_init_irq(void)
{
unsigned int i;
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
/* RUMI does not adhere to GIC spec by enabling STIs by default.
* Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
*/
if (!machine_is_msm8x60_sim())
writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
* as they are configured as level, which does not play nice with
* handle_percpu_irq.
*/
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
irq_set_handler(i, handle_percpu_irq);
}
}
/*
* Initializes the keyboard driver.
*/
void init_kbd(void)
{
/* Set the IRQ handler for the keyboard */
irq_set_handler(IRQ_KEYBOARD, handle_kbd_interrupt);
/* Enable the keyboard IRQ */
enable_irq_line(IRQ_KEYBOARD);
}
void __init bcmring_init_irq(void)
{
vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
/* special cases */
if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
irq_set_handler(IRQ_GPIO0, handle_simple_irq);
}
if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
irq_set_handler(IRQ_GPIO1, handle_simple_irq);
}
}
void __init arch_init_irq(void)
{
int i;
unsigned int gic_rev;
mips_cpu_irq_init();
if (cpu_has_vint)
set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
if (gcmp_present) {
GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
gic_present = 1;
}
if (gic_present) {
#if defined (CONFIG_MIPS_GIC_IPI)
gic_call_int_base = GIC_IPI_CALL_VPE0;
gic_resched_int_base = GIC_IPI_RESCHED_VPE0;
fill_ipi_map();
#endif
gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
printk("MIPS GIC RevID: %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
if (cpu_has_vint) {
pr_info("Setting up vectored interrupts\n");
set_vi_handler(2 + GIC_CPU_INT0, gic_irq_dispatch); // CPU
#if defined (CONFIG_MIPS_GIC_IPI)
set_vi_handler(2 + GIC_CPU_INT1, gic_irq_dispatch); // IPI resched
set_vi_handler(2 + GIC_CPU_INT2, gic_irq_dispatch); // IPI call
#endif
set_vi_handler(2 + GIC_CPU_INT3, gic_irq_dispatch); // FE
set_vi_handler(2 + GIC_CPU_INT4, gic_irq_dispatch); // PCIe
}
#if defined (CONFIG_MIPS_GIC_IPI)
set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2 |
STATUSF_IP4 | STATUSF_IP3);
/* setup ipi interrupts */
for (i = 0; i < nr_cpu_ids; i++) {
arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
}
#else
set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2);
#endif
/* set hardware irq, mapped to GIC shared (skip 0, 1, 2, 5, 7) */
for (i = 3; i <= 31; i++) {
if (i != 5 && i != 7)
irq_set_handler(MIPS_GIC_IRQ_BASE + i, handle_level_irq);
}
} else {
void init_IRQ(void)
{
int i;
for (i = 0; (i < NR_IRQS); i++) {
irq_set_chip(i, &intc_irq_chip);
irq_set_handler(i, handle_level_irq);
}
}
static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
irq_set_chip(virq, &cp_intc_irq_chip);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
irq_set_handler(virq, handle_edge_irq);
return 0;
}
void timer_setup()
{
//Set phase to 100hz
int divisor = 1193180 / 100;
outportb(0x43, 0x36);
outportb(0x40, divisor & 0xFF);
outportb(0x40, divisor >> 8);
//Set handler
irq_set_handler(0, timer_handler);
}
static int __init mcf_intc2_init(void)
{
int irq;
/* GPIO interrupt sources */
for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
irq_set_chip(irq, &intc2_irq_gpio_chip);
irq_set_handler(irq, handle_edge_irq);
}
return 0;
}
/**
* m68k_setup_irq_controller
* @chip: irq chip which controls specified irq
* @handle: flow handler which handles specified irq
* @irq: first irq to be managed by the controller
* @cnt: number of irqs to be managed by the controller
*
* Change the controller for the specified range of irq, which will be used to
* manage these irq. auto/user irq already have a default controller, which can
* be changed as well, but the controller probably should use m68k_irq_startup/
* m68k_irq_shutdown.
*/
void m68k_setup_irq_controller(struct irq_chip *chip,
irq_flow_handler_t handle, unsigned int irq,
unsigned int cnt)
{
int i;
for (i = 0; i < cnt; i++) {
irq_set_chip(irq + i, chip);
if (handle)
irq_set_handler(irq + i, handle);
}
}
static int s3c_irq_type(struct irq_data *data, unsigned int type)
{
switch (type) {
case IRQ_TYPE_NONE:
break;
case IRQ_TYPE_EDGE_RISING:
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_EDGE_BOTH:
irq_set_handler(data->irq, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
case IRQ_TYPE_LEVEL_HIGH:
irq_set_handler(data->irq, handle_level_irq);
break;
default:
pr_err("No such irq type %d", type);
return -EINVAL;
}
return 0;
}
void __init init_IRQ(void)
{
int irq;
mcf_maskimr(0xffffffff);
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_set_chip(irq, &intc_irq_chip);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
irq_set_handler(irq, handle_level_irq);
}
}
void
ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
{
unsigned int irq;
irq = vec;
BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
irq_set_status_flags(irq, IRQ_PER_CPU);
irq_set_chip(irq, &irq_type_ia64_lsapic);
if (action)
setup_irq(irq, action);
irq_set_handler(irq, handle_percpu_irq);
}
int __INIT__ at91sam926x_interrupt_init(void)
{
__u32 i, j;
__u32 irq;
at91_aic_init();
for (i = 0; i < 3; i++) {
for (j = 0; j < 32; j++) {
irq = 32 + ((i << 5) | j);
irq_assoc_intctl(irq, &at91sam926x_gpio_intctrl);
irq_set_handler(irq, irq_handle_simple, 0);
}
irq_set_handler(PIO_IRQ_OFFSET + i, at91sam926x_gpio_irqparse, 1);
}
irq_enable(); // fixme
return 0;
}
/*
* At some point in the boot process, we get asked to set up our timing
* infrastructure. The kernel doesn't expect timer interrupts before this, but
* we cleverly initialized the "blocked_interrupts" field of "struct
* lguest_data" so that timer interrupts were blocked until now.
*/
static void lguest_time_init(void)
{
/* Set up the timer interrupt (0) to go to our simple timer routine */
irq_set_handler(0, lguest_time_irq);
clocksource_register_hz(&lguest_clock, NSEC_PER_SEC);
/* We can't set cpumask in the initializer: damn C limitations! Set it
* here and register our timer device. */
lguest_clockevent.cpumask = cpumask_of(0);
clockevents_register_device(&lguest_clockevent);
/* Finally, we unblock the timer interrupt. */
clear_bit(0, lguest_data.blocked_interrupts);
}
