int snd_record_refill(short *buffer)
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(0);
if(record_level >= RECORD_BUFQ_SIZE) {
irq_setmask(oldmask);
printf("SND: record bufq overflow\n");
return 0;
}
record_queue[record_produce] = buffer;
record_produce = (record_produce + 1) & RECORD_BUFQ_MASK;
record_level++;
if(record_overrun) {
record_overrun = 0;
record_start(buffer);
}
irq_setmask(oldmask);
return 1;
}
int slowout_queue(unsigned int duration, unsigned int mask)
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(oldmask & (~IRQ_TIMER1));
if(level >= OPQ_SIZE) {
irq_setmask(oldmask);
printf("SLO: opq overflow\n");
return 0;
}
queue[produce].duration = duration;
queue[produce].mask = mask;
if(cts) {
cts = 0;
slowout_start(&queue[produce]);
}
produce = (produce + 1) & OPQ_MASK;
level++;
irq_setmask(oldmask);
return 1;
}
int snd_play_refill(short *buffer)
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(0);
if(play_level >= PLAY_BUFQ_SIZE) {
irq_setmask(oldmask);
printf("SND: play bufq overflow\n");
return 0;
}
play_queue[play_produce] = buffer;
play_produce = (play_produce + 1) & PLAY_BUFQ_MASK;
play_level++;
if(play_underrun) {
play_underrun = 0;
play_start(buffer);
}
irq_setmask(oldmask);
return 1;
}
int pfpu_submit_task(struct pfpu_td *td)
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(oldmask & (~IRQ_PFPU));
if(level >= PFPU_TASKQ_SIZE) {
irq_setmask(oldmask);
printf("FPU: taskq overflow\n");
return 0;
}
queue[produce] = td;
produce = (produce + 1) & PFPU_TASKQ_MASK;
level++;
if(cts) {
cts = 0;
pfpu_start(td);
}
irq_setmask(oldmask);
return 1;
}
void rpipe_swap_bottom_half()
{
unsigned short *b;
unsigned int oldmask;
/* Swap texture buffers */
b = tex_backbuffer;
tex_backbuffer = tex_frontbuffer;
tex_frontbuffer = b;
/* Update display */
vga_swap_buffers();
/* Update statistics */
oldmask = irq_getmask();
irq_setmask(oldmask & ~(IRQ_TIMER0));
frames++;
irq_setmask(oldmask);
/* Ready to process the next frame ! */
queue[consume]->callback(queue[consume]);
consume = (consume + 1) & RPIPE_FRAMEQ_MASK;
level--;
if(level > 0)
rpipe_start(queue[consume]);
else
cts = 1;
}
void snd_record_stop()
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(oldmask & (~IRQ_AC97DMAW));
CSR_AC97_UCTL = 0; /* this also acks any pending IRQ in the AC97 core */
irq_ack(IRQ_AC97DMAW);
irq_setmask(oldmask);
}
void snd_record_stop()
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(0);
CSR_AC97_UCTL = 0;
record_overrun = 0;
irq_ack(IRQ_AC97DMAW);
irq_setmask(oldmask);
}
void snd_play_stop()
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(0);
CSR_AC97_DCTL = 0;
play_underrun = 0;
irq_ack(IRQ_AC97DMAR);
irq_setmask(oldmask);
}
void cpustats_enter()
{
unsigned int oldmask = 0;
oldmask = irq_getmask();
irq_setmask(0);
enter_count++;
if(enter_count == 1)
time_get(&first_enter);
irq_setmask(oldmask);
}
void uart_write(char c)
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(0);
while (!(readb(&uart->lsr) & (LM32_UART_LSR_THRR | LM32_UART_LSR_TEMT)))
;
writeb(c, &uart->rxtx);
irq_setmask(oldmask);
}
void putsnonl(const char *s)
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(IRQ_UART); // HACK: prevent UART data loss
while(*s) {
writechar(*s);
s++;
}
irq_setmask(oldmask);
}
void uart_write(char c)
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(0);
if(tx_cts) {
tx_cts = 0;
CSR_UART_RXTX = c;
} else {
tx_buf[tx_produce] = c;
tx_produce = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
}
irq_setmask(oldmask);
}
void hdmi_in1_init_video(int hres, int vres)
{
unsigned int mask;
hdmi_in1_clocking_pll_reset_write(1);
hdmi_in1_connected = hdmi_in1_locked = 0;
hdmi_in1_hres = hres; hdmi_in1_vres = vres;
hdmi_in1_dma_frame_size_write(hres*vres*2);
hdmi_in1_fb_slot_indexes[0] = 0;
hdmi_in1_dma_slot0_address_write(hdmi_in1_framebuffer_base(0));
hdmi_in1_dma_slot0_status_write(DVISAMPLER_SLOT_LOADED);
hdmi_in1_fb_slot_indexes[1] = 1;
hdmi_in1_dma_slot1_address_write(hdmi_in1_framebuffer_base(1));
hdmi_in1_dma_slot1_status_write(DVISAMPLER_SLOT_LOADED);
hdmi_in1_next_fb_index = 2;
hdmi_in1_dma_ev_pending_write(hdmi_in1_dma_ev_pending_read());
hdmi_in1_dma_ev_enable_write(0x3);
mask = irq_getmask();
mask |= 1 << HDMI_IN1_INTERRUPT;
irq_setmask(mask);
hdmi_in1_fb_index = 3;
}
int main(void)
{
irq_setmask(0);
irq_setie(1);
uart_init();
#ifdef CSR_HDMI_OUT0_I2C_W_ADDR
hdmi_out0_i2c_init();
#endif
#ifdef CSR_HDMI_OUT1_I2C_W_ADDR
hdmi_out1_i2c_init();
#endif
puts("\r\nHDMI2USB firmware http://timvideos.us/");
print_version();
fx2_reset_out_write(1);
config_init();
time_init();
processor_init();
processor_start(config_get(CONFIG_KEY_RESOLUTION));
// Set HDMI Output 0 to be pattern
#ifdef CSR_HDMI_OUT0_BASE
processor_set_hdmi_out0_source(VIDEO_IN_PATTERN);
#endif
// Set HDMI Output 1 to be pattern
#ifdef CSR_HDMI_OUT1_BASE
processor_set_hdmi_out1_source(VIDEO_IN_PATTERN);
#endif
processor_update();
// Reboot the FX2 chip into HDMI2USB mode
#ifdef CSR_FX2_RESET_OUT_ADDR
//fx2_init();
#endif
// Set Encoder to be pattern
#ifdef ENCODER_BASE
processor_set_encoder_source(VIDEO_IN_PATTERN);
encoder_enable(1);
processor_update();
#endif
ci_prompt();
while(1) {
processor_service();
ci_service();
#ifdef CSR_FX2_RESET_OUT_ADDR
//fx2_service(true);
#endif
/* XXX FIX DDR conflict between DMA and L2 cache */
#if 0
pattern_service();
#endif
}
return 0;
}
int main(void)
{
irq_setmask(0);
irq_setie(1);
uart_init();
puts("\nHDMI2USB firmware http://timvideos.us/");
printf("Board's DNA: %016x\n", dna_id_read());
printf("Revision %08x built "__DATE__" "__TIME__"\n", MSC_GIT_ID);
ci_prompt();
config_init();
time_init();
processor_init();
processor_start(config_get(CONFIG_KEY_RESOLUTION));
while(1) {
processor_service();
ci_service();
/* XXX FIX DDR conflict between DMA and L2 cache */
#if 0
pattern_service();
#endif
}
return 0;
}
void dvisampler_init_video(int hres, int vres)
{
unsigned int mask;
dvisampler_clocking_pll_reset_write(1);
dvisampler_connected = dvisampler_locked = 0;
dvisampler_hres = hres; dvisampler_vres = vres;
dvisampler_dma_frame_size_write(hres*vres*2);
dvisampler_fb_slot_indexes[0] = 0;
dvisampler_dma_slot0_address_write(dvisampler_framebuffer_base(0));
dvisampler_dma_slot0_status_write(DVISAMPLER_SLOT_LOADED);
dvisampler_fb_slot_indexes[1] = 1;
dvisampler_dma_slot1_address_write(dvisampler_framebuffer_base(1));
dvisampler_dma_slot1_status_write(DVISAMPLER_SLOT_LOADED);
dvisampler_next_fb_index = 2;
dvisampler_dma_ev_pending_write(dvisampler_dma_ev_pending_read());
dvisampler_dma_ev_enable_write(0x3);
mask = irq_getmask();
mask |= 1 << DVISAMPLER_INTERRUPT;
irq_setmask(mask);
fb_fi_base0_write(dvisampler_framebuffer_base(3));
}
int main(int i, char **c)
{
char buffer[64];
int sdr_ok;
irq_setmask(0);
irq_setie(1);
uart_init();
puts("\nMiSoC BIOS\n"
"(c) Copyright 2007-2016 M-Labs Limited\n"
"Built "__DATE__" "__TIME__"\n");
crcbios();
#ifdef CSR_ETHMAC_BASE
eth_init();
#endif
#ifdef CSR_DFII_BASE
sdr_ok = sdrinit();
#else
sdr_ok = 1;
#endif
if(sdr_ok)
boot_sequence();
else
printf("Memory initialization failed\n");
while(1) {
putsnonl("\e[1mBIOS>\e[0m ");
readstr(buffer, 64);
do_command(buffer);
}
return 0;
}
int puts(const char *s)
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(IRQ_UART); // HACK: prevent UART data loss
while(*s) {
writechar(*s);
s++;
}
writechar('\n');
irq_setmask(oldmask);
return 1;
}
void uart_init(void)
{
uint32_t mask;
uint8_t value;
rx_produce = 0;
rx_consume = 0;
irq_ack(IRQ_UART);
/* enable UART interrupts */
writeb(LM32_UART_IER_RBRI, &uart->ier);
mask = irq_getmask();
mask |= IRQ_UART;
irq_setmask(mask);
/* Line control 8 bit, 1 stop, no parity */
writeb(LM32_UART_LCR_8BIT, &uart->lcr);
/* Modem control, DTR = 1, RTS = 1 */
writeb(LM32_UART_MCR_DTR | LM32_UART_MCR_RTS, &uart->mcr);
/* Set baud rate */
value = (CPU_FREQUENCY / UART_BAUD_RATE) & 0xff;
writeb(value, &uart->divl);
value = (CPU_FREQUENCY / UART_BAUD_RATE) >> 8;
writeb(value, &uart->divh);
}
void snd_init()
{
unsigned int codec_id;
unsigned int mask;
snd_cr_request = 0;
snd_cr_reply = 0;
CSR_AC97_DCTL = 0;
CSR_AC97_UCTL = 0;
mask = irq_getmask();
mask |= IRQ_AC97CRREQUEST|IRQ_AC97CRREPLY|IRQ_AC97DMAR|IRQ_AC97DMAW;
irq_setmask(mask);
codec_id = snd_ac97_read(0x00);
if(codec_id == 0x0d50)
printf("SND: found LM4550 AC'97 codec\n");
else
printf("SND: warning, unknown codec found (ID:%04x)\n", codec_id);
/* Unmute and set volumes */
/* TODO: API for this */
snd_ac97_write(0x02, 0x0000);
snd_ac97_write(0x04, 0x0f0f);
snd_ac97_write(0x18, 0x0000);
snd_ac97_write(0x0e, 0x0000);
snd_ac97_write(0x1c, 0x0f0f);
snd_play_empty();
snd_record_empty();
printf("SND: initialization complete\n");
}
__attribute__((noreturn)) void reboot()
{
uart_force_sync(1); /* flush UART buffers */
irq_setmask(0);
irq_enable(0);
CSR_SYSTEM_ID = 1; /* Writing to CSR_SYSTEM_ID causes a system reset */
while(1);
}
static void __attribute__((noreturn)) boot(unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int addr)
{
vga_blank();
uart_force_sync(1);
irq_setmask(0);
irq_enable(0);
boot_helper(r1, r2, r3, r4, addr);
while(1);
}
void cpustats_leave()
{
unsigned int oldmask = 0;
oldmask = irq_getmask();
irq_setmask(0);
enter_count--;
if(enter_count == 0) {
struct timestamp ts;
struct timestamp diff;
time_get(&ts);
time_diff(&diff, &ts, &first_enter);
time_add(&acc, &diff);
}
irq_setmask(oldmask);
}
static void __attribute__((noreturn)) boot(unsigned int r1, unsigned int r2, unsigned int r3, unsigned int addr)
{
printf("Executing booted program.\n");
uart_sync();
irq_setmask(0);
irq_setie(0);
flush_cpu_icache();
boot_helper(r1, r2, r3, addr);
while(1);
}
int main(void)
{
irq_setmask(0);
irq_setie(1);
uart_init();
puts("Raw DVI dump software built "__DATE__" "__TIME__"\n");
dvidump();
return 0;
}
void uart_write(char c)
{
unsigned int oldmask;
if(irq_getie()) {
while(tx_level == UART_RINGBUFFER_SIZE_TX);
}
oldmask = irq_getmask();
irq_setmask(0);
if(tx_cts) {
tx_cts = 0;
uart_rxtx_write(c);
} else {
tx_buf[tx_produce] = c;
tx_produce = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
tx_level++;
}
irq_setmask(oldmask);
}
void uart_write(char c)
{
unsigned int oldmask;
oldmask = irq_getmask();
irq_setmask(0);
if(force_sync) {
CSR_UART_RXTX = c;
while(!(CSR_UART_STAT & UART_STAT_THRE));
} else {
if(tx_cts) {
tx_cts = 0;
CSR_UART_RXTX = c;
} else {
tx_buf[tx_produce] = c;
tx_produce = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
}
}
irq_setmask(oldmask);
}
void hdmi_in1_disable(void)
{
unsigned int mask;
mask = irq_getmask();
mask &= ~(1 << HDMI_IN1_INTERRUPT);
irq_setmask(mask);
hdmi_in1_dma_slot0_status_write(DVISAMPLER_SLOT_EMPTY);
hdmi_in1_dma_slot1_status_write(DVISAMPLER_SLOT_EMPTY);
hdmi_in1_clocking_pll_reset_write(1);
}
void dvisampler_disable(void)
{
unsigned int mask;
mask = irq_getmask();
mask &= ~(1 << DVISAMPLER_INTERRUPT);
irq_setmask(mask);
dvisampler_dma_slot0_status_write(DVISAMPLER_SLOT_EMPTY);
dvisampler_dma_slot1_status_write(DVISAMPLER_SLOT_EMPTY);
dvisampler_clocking_pll_reset_write(1);
}
void up_enable_irq(int irq)
{
irqstate_t flags;
DEBUGASSERT(irq >= 0 && irq < NR_IRQS);
/* Ignore any attempt to enable software interrupts */
if (irq < LM32_NINTERRUPTS)
{
/* Enable interrupts by setting the bit that corresponds to the irq */
flags = irq_getmask();
flags |= (1 << irq);
irq_setmask(flags);
}
}
