static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node, struct module *owner) { int cpu; desc->irq_data.irq = irq; desc->irq_data.chip = &no_irq_chip; desc->irq_data.chip_data = NULL; desc->irq_data.handler_data = NULL; desc->irq_data.msi_desc = NULL; irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS); irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); desc->handle_irq = handle_bad_irq; desc->depth = 1; desc->irq_count = 0; desc->irqs_unhandled = 0; desc->name = NULL; desc->owner = owner; for_each_possible_cpu(cpu) *per_cpu_ptr(desc->kstat_irqs, cpu) = 0; desc_smp_init(desc, node); }
void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) { unsigned long flags, trigger, tmp; struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); if (!desc) return; /* * Warn when a driver sets the no autoenable flag on an already * active interrupt. */ WARN_ON_ONCE(!desc->depth && (set & _IRQ_NOAUTOEN)); irq_settings_clr_and_set(desc, clr, set); trigger = irqd_get_trigger_type(&desc->irq_data); irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); if (irq_settings_has_no_balance_set(desc)) irqd_set(&desc->irq_data, IRQD_NO_BALANCING); if (irq_settings_is_per_cpu(desc)) irqd_set(&desc->irq_data, IRQD_PER_CPU); if (irq_settings_can_move_pcntxt(desc)) irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); if (irq_settings_is_level(desc)) irqd_set(&desc->irq_data, IRQD_LEVEL); tmp = irq_settings_get_trigger_mask(desc); if (tmp != IRQ_TYPE_NONE) trigger = tmp; irqd_set(&desc->irq_data, trigger); irq_put_desc_unlock(desc, flags); }
void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) { unsigned long flags; struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); if (!desc) return; irq_settings_clr_and_set(desc, clr, set); irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); if (irq_settings_has_no_balance_set(desc)) irqd_set(&desc->irq_data, IRQD_NO_BALANCING); if (irq_settings_is_per_cpu(desc)) irqd_set(&desc->irq_data, IRQD_PER_CPU); if (irq_settings_can_move_pcntxt(desc)) irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); if (irq_settings_is_level(desc)) irqd_set(&desc->irq_data, IRQD_LEVEL); irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); irq_put_desc_unlock(desc, flags); }
// ARM10C 20141004 // irq: 0, desc: kmem_cache#28-o0, node: 0, owner: null static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node, struct module *owner) { int cpu; // desc->irq_data.irq: (kmem_cache#28-o0)->irq_data.irq, irq: 0 desc->irq_data.irq = irq; // desc->irq_data.irq: (kmem_cache#28-o0)->irq_data.irq: 0 // desc->irq_data.chip: (kmem_cache#28-o0)->irq_data.chip desc->irq_data.chip = &no_irq_chip; // desc->irq_data.chip: (kmem_cache#28-o0)->irq_data.chip: &no_irq_chip // desc->irq_data.chip_data: (kmem_cache#28-o0)->irq_data.chip_data desc->irq_data.chip_data = NULL; // desc->irq_data.chip_data: (kmem_cache#28-o0)->irq_data.chip_data: NULL // desc->irq_data.handler_data: (kmem_cache#28-o0)->irq_data.handler_data desc->irq_data.handler_data = NULL; // desc->irq_data.handler_data: (kmem_cache#28-o0)->irq_data.handler_data: NULL // desc->irq_data.msi_desc: (kmem_cache#28-o0)->irq_data.msi_desc desc->irq_data.msi_desc = NULL; // desc->irq_data.msi_desc: (kmem_cache#28-o0)->irq_data.msi_desc: NULL // desc: kmem_cache#28-o0, 0xFFFFFFFF, _IRQ_DEFAULT_INIT_FLAGS: 0xc00 irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS); // irq_settings_clr_and_set에서 한일: // desc->status_use_accessors: (kmem_cache#28-o0)->status_use_accessors: 0xc00 // &desc->irq_data: &(kmem_cache#28-o0)->irq_data, IRQD_IRQ_DISABLED: 0x10000 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); // irqd_set에서 한일: // d->state_use_accessors: (&(kmem_cache#28-o0)->irq_data)->state_use_accessors: 0x10000 // desc->handle_irq: (kmem_cache#28-o0)->handle_irq desc->handle_irq = handle_bad_irq; // desc->handle_irq: (kmem_cache#28-o0)->handle_irq: handle_bad_irq // desc->depth: (kmem_cache#28-o0)->depth desc->depth = 1; // desc->depth: (kmem_cache#28-o0)->depth: 1 // desc->irq_count: (kmem_cache#28-o0)->irq_count desc->irq_count = 0; // desc->irq_count: (kmem_cache#28-o0)->irq_count: 0 // desc->irqs_unhandled: (kmem_cache#28-o0)->irqs_unhandled desc->irqs_unhandled = 0; // desc->irqs_unhandled: (kmem_cache#28-o0)->irqs_unhandled: 0 // desc->name: (kmem_cache#28-o0)->name desc->name = NULL; // desc->name: (kmem_cache#28-o0)->name: NULL // desc->owner: (kmem_cache#28-o0)->owner, owner: null desc->owner = owner; // desc->owner: (kmem_cache#28-o0)->owner: null for_each_possible_cpu(cpu) // for ((cpu) = -1; (cpu) = cpumask_next((cpu), (cpu_possible_mask)), (cpu) < nr_cpu_ids; ) // desc->kstat_irqs: (kmem_cache#28-o0)->kstat_irqs, cpu: 0 *per_cpu_ptr(desc->kstat_irqs, cpu) = 0; // [pcp0] (kmem_cache#28-o0)->kstat_irqs: 0 // cpu: 1 .. 3 수행 // desc: kmem_cache#28-o0, node: 0 desc_smp_init(desc, node); // desc_smp_init에서 한일: // desc->irq_data.node: (kmem_cache#28-o0)->irq_data.node: 0 // desc->irq_data.affinity: (kmem_cache#28-o0)->irq_data.affinity.bits[0]: 0xF }