void parseCodeStore(Instruction codeStore[]) { fprintf(stacktrace_file, "\t\t\t\tpc\tbp\tsp\tstack\n"); fprintf(stacktrace_file, "Initial values\t\t\t\t\t%d\t%d\t%d\n", sp, bp, sp); while(true) { Fetch(); Execute(); if(isHalt(IR) || HALT) break; } }
void CpuRiscV_Functional::updateDebugPort() { CpuContextType *pContext = getpContext(); DsuMapType::udbg_type::debug_region_type::control_reg ctrl; DebugPortTransactionType *trans = dport.trans; trans->rdata = 0; switch (trans->region) { case 0: // CSR trans->rdata = pContext->csr[trans->addr]; if (trans->write) { pContext->csr[trans->addr] = trans->wdata; } break; case 1: // IRegs if (trans->addr < Reg_Total) { trans->rdata = pContext->regs[trans->addr]; if (trans->write) { pContext->regs[trans->addr] = trans->wdata; } } else if (trans->addr == Reg_Total) { /** Read only register */ trans->rdata = pContext->pc; } else if (trans->addr == (Reg_Total + 1)) { trans->rdata = pContext->npc; if (trans->write) { pContext->npc = trans->wdata; } } break; case 2: // Control switch (trans->addr) { case 0: ctrl.val = trans->wdata; if (trans->write) { if (ctrl.bits.halt) { halt(); } else if (ctrl.bits.stepping) { step(dport.stepping_mode_steps); } else { go(); } } else { ctrl.val = 0; ctrl.bits.halt = isHalt() ? 1: 0; ctrl.bits.core_id = 0; } trans->rdata = ctrl.val; break; case 1: trans->rdata = dport.stepping_mode_steps; if (trans->write) { dport.stepping_mode_steps = trans->wdata; } break; case 2: trans->rdata = pContext->step_cnt; break; case 3: trans->rdata = pContext->step_cnt; break; case 4: if (trans->write) { addBreakpoint(trans->wdata); } break; case 5: if (trans->write) { removeBreakpoint(trans->wdata); } break; default:; } break; default:; } dport.cb->nb_response_debug_port(dport.trans); }