static void lpc_init(device_t dev)
{
u8 byte;
u32 dword;
device_t sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);
/* Initialize isa dma */
#if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");
#else
isa_dma_init();
#endif
/* Enable DMA transaction on the LPC bus */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* Disable the timeout mechanism on LPC */
byte = pci_read_config8(dev, 0x48);
byte &= ~(1 << 7);
pci_write_config8(dev, 0x48, byte);
/* Disable LPC MSI Capability */
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
pci_write_config8(dev, 0x78, byte);
}
static void lpc_init(device_t dev)
{
u8 byte;
u32 dword;
device_t sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);
/* Initialize isa dma */
isa_dma_init();
/* RPR 7.2 Enable DMA transaction on the LPC bus */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* RPR 7.3 Disable the timeout mechanism on LPC */
byte = pci_read_config8(dev, 0x48);
byte &= ~(1 << 7);
pci_write_config8(dev, 0x48, byte);
/* RPR 7.5 Disable LPC MSI Capability */
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
pci_write_config8(dev, 0x78, byte);
cmos_check_update_date();
}
static void lpc_init(struct device *dev)
{
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
i82801ax_enable_acpi(dev);
/* IO APIC initialization. */
i82801ax_enable_ioapic(dev);
i82801ax_enable_serial_irqs(dev);
/* Setup the PIRQ. */
i82801ax_pirq_init(dev);
/* Setup power options. */
i82801ax_power_options(dev);
/* Set the state of the GPIO lines. */
gpio_init(dev);
/* Initialize the real time clock. */
i82801ax_rtc_init(dev);
/* Route DMA. */
i82801ax_lpc_route_dma(dev, 0xff);
/* Initialize ISA DMA. */
isa_dma_init();
/* Setup decode ports and LPC I/F enables. */
i82801ax_lpc_decode_en(dev);
}
static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: lpc_init\n");
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
pch_enable_ioapic(dev);
pch_enable_serial_irqs(dev);
/* Setup the PIRQ. */
pch_pirq_init(dev);
/* Setup power options. */
pch_power_options(dev);
/* Initialize power management */
switch (pch_silicon_type()) {
case PCH_TYPE_CPT: /* CougarPoint */
cpt_pm_init(dev);
break;
case PCH_TYPE_PPT: /* PantherPoint */
ppt_pm_init(dev);
break;
default:
printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
}
/* Set the state of the GPIO lines. */
//gpio_init(dev);
/* Initialize the real time clock. */
pch_rtc_init(dev);
/* Initialize ISA DMA. */
isa_dma_init();
/* Initialize the High Precision Event Timers, if present. */
enable_hpet();
/* Initialize Clock Gating */
enable_clock_gating(dev);
setup_i8259();
/* The OS should do this? */
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
pch_disable_smm_only_flashing(dev);
#if CONFIG_HAVE_SMI_HANDLER
pch_lock_smm(dev);
#endif
pch_fixups(dev);
}
static void lpc_init(device_t dev)
{
/* Initialize the real time clock */
cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
}
static void lpc_init(device_t dev)
{
u8 byte;
u32 dword;
device_t sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);
/* Initialize isa dma */
isa_dma_init();
/* Enable DMA transaction on the LPC bus */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* Disable the timeout mechanism on LPC */
byte = pci_read_config8(dev, 0x48);
byte &= ~(1 << 7);
pci_write_config8(dev, 0x48, byte);
/* Disable LPC MSI Capability */
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going
on on LPC, it holds PCI grant, so no LPC slave cycle can
interrupt and visit LPC. */
pci_write_config8(dev, 0x78, byte);
/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */
/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
byte = pci_read_config8(dev, 0xBB);
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
cmos_check_update_date();
/* Initialize the real time clock.
* The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
* 1 tells cmos_init to always initialize the CMOS.
*/
cmos_init(0);
/* Initialize i8259 pic */
setup_i8259 ();
/* Initialize i8254 timers */
setup_i8254 ();
}
void
isa_attach_hook(device_t parent, device_t self, struct isabus_attach_args *iba)
{
/*
* Since we can only have one ISA bus, we just use a single
* statically allocated ISA chipset structure. Pass it up
* now.
*/
iba->iba_ic = &isa_chipset_tag;
#if NISADMA > 0
isa_dma_init();
#endif
}
static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "i82801gx: lpc_init\n");
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
i82801gx_enable_ioapic(dev);
i82801gx_enable_serial_irqs(dev);
/* Setup the PIRQ. */
i82801gx_pirq_init(dev);
/* Setup power options. */
i82801gx_power_options(dev);
/* Configure Cx state registers */
i82801gx_configure_cstates(dev);
/* Set the state of the GPIO lines. */
//gpio_init(dev);
/* Initialize the real time clock. */
i82801gx_rtc_init(dev);
/* Initialize ISA DMA. */
isa_dma_init();
/* Initialize the High Precision Event Timers, if present. */
enable_hpet();
/* Initialize Clock Gating */
enable_clock_gating();
setup_i8259();
/* The OS should do this? */
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
#if CONFIG_HAVE_SMI_HANDLER
i82801gx_lock_smm(dev);
#endif
i82801gx_spi_init();
i82801gx_fixups(dev);
}
static void lpc_init(struct device *dev)
{
uint8_t byte;
int pwr_on=-1;
int nmi_option;
/* IO APIC initialization */
i82801cx_enable_ioapic(dev);
i82801cx_enable_serial_irqs(dev);
/* power after power fail */
/* FIXME this doesn't work! */
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
*/
byte = pci_read_config8(dev, GEN_PMCON_3);
if (pwr_on)
byte &= ~1; // Return to S0 (boot) after power is re-applied
else
byte |= 1; // Return to S5
pci_write_config8(dev, GEN_PMCON_3, byte);
printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
/* Set up NMI on errors */
byte = inb(0x61);
byte &= ~(1 << 3); /* IOCHK# NMI Enable */
byte &= ~(1 << 2); /* PCI SERR# Enable */
outb(byte, 0x61);
byte = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
outb(byte, 0x70);
}
/* Initialize the real time clock */
i82801cx_rtc_init(dev);
i82801cx_lpc_route_dma(dev, 0xff);
/* Initialize isa dma */
isa_dma_init();
i82801cx_1f0_misc(dev);
}
static void lpc_init(struct device *dev)
{
uint8_t byte;
int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
i82801ex_general_cntl(dev);
/* IO APIC initialization. */
setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IO APIC ID.
i82801ex_enable_serial_irqs(dev);
i82801ex_pci_dma_cfg(dev);
i82801ex_enable_lpc(dev);
/* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00);
get_option(&pwr_on, "power_on_after_fail");
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {
byte |= 1;
}
pci_write_config8(dev, 0xa4, byte);
printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
/* Set up the PIRQ */
i82801ex_pirq_init(dev);
/* Set the state of the gpio lines */
i82801ex_gpio_init(dev);
/* Initialize the real time clock */
cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
/* Disable IDE (needed when sata is enabled) */
pci_write_config8(dev, 0xf2, 0x60);
enable_hpet(dev);
}
void lpc_soc_init(struct device *dev)
{
/* Legacy initialization */
isa_dma_init();
pch_misc_init();
/* Enable CLKRUN_EN for power gating LPC */
lpc_enable_pci_clk_cntl();
/* Set LPC Serial IRQ mode */
if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
else
lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */
pch_enable_ioapic(dev);
soc_pch_pirq_init(dev);
setup_i8259();
i8259_configure_irq_trigger(9, 1);
clock_gate_8254(dev);
soc_mirror_dmi_pcr_io_dec();
}
static void lpc_init(device_t dev)
{
uint8_t byte;
uint8_t byte_old;
int on;
int nmi_option;
printk(BIOS_DEBUG, "LPC_INIT -------->\n");
pc_keyboard_init();
lpc_usb_legacy_init(dev);
lpc_common_init(dev);
/* power after power fail */
on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
byte |= 0x40;
}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if(on) {
uint16_t pm10_bar;
uint32_t dword;
pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10);
on = 8-on;
printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
(on*12)+(on>>1),(on&1)*5);
}
/* Enable Error reporting */
/* Set up sync flood detected */
byte = pci_read_config8(dev, 0x47);
byte |= (1 << 1);
pci_write_config8(dev, 0x47, byte);
/* Set up NMI on errors */
byte = inb(0x70); // RTC70
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
outb(byte, 0x70);
}
/* Initialize the real time clock */
rtc_init(0);
/* Initialize isa dma */
isa_dma_init();
printk(BIOS_DEBUG, "LPC_INIT <--------\n");
}
u_int
initarm(void *arg)
{
ofw_handle_t ofw_handle = arg;
paddr_t pclean;
vaddr_t isa_io_virtaddr, isa_mem_virtaddr;
paddr_t isadmaphysbufs;
extern char shark_fiq[], shark_fiq_end[];
/* Don't want to get hit with interrupts 'til we're ready. */
(void)disable_interrupts(I32_bit | F32_bit);
set_cpufuncs();
/* XXX - set these somewhere else? -JJK */
boothowto = 0;
/* Init the OFW interface. */
/* MUST do this before invoking any OFW client services! */
ofw_init(ofw_handle);
/* Configure ISA stuff: must be done before consinit */
ofw_configisa(&isa_io_physaddr, &isa_mem_physaddr);
/* Map-in ISA I/O and memory space. */
/* XXX - this should be done in the isa-bus attach routine! -JJK */
isa_mem_virtaddr = ofw_map(isa_mem_physaddr, L1_S_SIZE, 0);
isa_io_virtaddr = ofw_map(isa_io_physaddr, L1_S_SIZE, 0);
/* Set-up the ISA system: must be done before consinit */
isa_init(isa_io_virtaddr, isa_mem_virtaddr);
/* Initialize the console (which will call into OFW). */
/* This will allow us to see panic messages and other printf output. */
consinit();
/* Get boot info and process it. */
ofw_getbootinfo(&boot_file, &boot_args);
process_kernel_args();
ofw_configisadma(&isadmaphysbufs);
#if (NISADMA > 0)
isa_dma_init();
#endif
/* allocate a cache clean space */
if ((pclean = ofw_getcleaninfo()) != -1) {
sa1_cache_clean_addr = ofw_map(pclean, 0x4000 * 2,
L2_B | L2_C);
sa1_cache_clean_size = 0x4000;
}
/* Configure memory. */
ofw_configmem();
/*
* Set-up stacks.
* The kernel stack for SVC mode will be updated on return
* from this routine.
*/
set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + PAGE_SIZE);
set_stackptr(PSR_UND32_MODE, undstack.pv_va + PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + PAGE_SIZE);
/* Set-up exception handlers. */
/*
* Take control of selected vectors from OFW.
* We take: undefined, swi, pre-fetch abort, data abort, addrexc,
* irq, fiq
* OFW retains: reset
*/
arm32_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL & ~ARM_VEC_RESET);
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address =
(u_int)undefinedinstruction_bounce; /* why is this needed? -JJK */
/* Initialise the undefined instruction handlers. */
undefined_init();
/* Now for the SHARK-specific part of the FIQ set-up */
shark_fiqhandler.fh_func = shark_fiq;
shark_fiqhandler.fh_size = shark_fiq_end - shark_fiq;
shark_fiqhandler.fh_flags = 0;
shark_fiqhandler.fh_regs = &shark_fiqregs;
shark_fiqregs.fr_r8 = isa_io_virtaddr;
shark_fiqregs.fr_r9 = 0; /* no routine right now */
shark_fiqregs.fr_r10 = 0; /* no arg right now */
shark_fiqregs.fr_r11 = 0; /* scratch */
shark_fiqregs.fr_r12 = 0; /* scratch */
shark_fiqregs.fr_r13 = 0; /* must set a stack when r9 is set! */
if (fiq_claim(&shark_fiqhandler))
panic("Cannot claim FIQ vector.");
#if NKSYMS || defined(DDB) || defined(MODULAR)
#ifndef __ELF__
{
struct exec *kernexec = (struct exec *)KERNEL_TEXT_BASE;
extern int end;
extern char *esym;
ksyms_addsyms_elf(kernexec->a_syms, &end, esym);
}
#endif /* __ELF__ */
#endif /* NKSYMS || defined(DDB) || defined(MODULAR) */
#ifdef DDB
db_machine_init();
if (boothowto & RB_KDB)
Debugger();
#endif
/* Return the new stackbase. */
return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
}
