static void jmr3927_board_init() { char *argptr; #ifdef CONFIG_PCI mips_pci_io_base = JMR3927_PCIIO; mips_pci_io_size = JMR3927_PCIIO_SIZE; mips_pci_mem_base = JMR3927_PCIMEM; mips_pci_mem_size = JMR3927_PCIMEM_SIZE; #endif tx3927_setup(); #ifdef CONFIG_VT conswitchp = &dummy_con; #endif if (jmr3927_have_isac()) { #ifdef CONFIG_FB_E1355 argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "video=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " video=e1355fb:crt16h"); } #endif #ifdef CONFIG_BLK_DEV_IDE /* overrides PCI-IDE */ #endif #ifdef CONFIG_PC_KEYB //not yet kbd_ops = &jmr3927_kbd_ops; #endif } #ifdef USE_RTC_DS1742 if (jmr3927_have_nvram()) { rtc_ops = &jmr3927_rtc_ops; } #endif /* SIO0 DTR on */ jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); jmr3927_led_set(0); if (jmr3927_have_isac()) jmr3927_io_led_set(0); printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, jmr3927_dipsw1(), jmr3927_dipsw2(), jmr3927_dipsw3(), jmr3927_dipsw4()); if (jmr3927_have_isac()) printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n", jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK, jmr3927_io_dipsw()); }
static void __init jmr3927_board_init(void) { tx3927_setup(); /* SIO0 DTR on */ jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); jmr3927_led_set(0); printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, jmr3927_dipsw1(), jmr3927_dipsw2(), jmr3927_dipsw3(), jmr3927_dipsw4()); }
static inline void do_reset(void) { #if 1 /* Resetting PCI bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ mdelay(1); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); #endif jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); }
static void __init jmr3927_board_init(void) { txx9_cpu_clock = JMR3927_CORECLK; tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL; tx3927_ccfgptr->pcfg |= TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL | (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1)); tx3927_setup(); __raw_writel(0x0000f000, &tx3927_pioptr->dir); gpio_request(11, "dipsw1"); gpio_request(10, "dipsw2"); jmr3927_pci_setup(); jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); jmr3927_led_set(0); printk(KERN_INFO "JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n", jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK, jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK, jmr3927_dipsw1(), jmr3927_dipsw2(), jmr3927_dipsw3(), jmr3927_dipsw4()); }
static void jmr3927_machine_restart(char *command) { local_irq_disable(); #if 1 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); mdelay(1); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); #endif jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); (*_machine_halt)(); }
static void jmr3927_machine_restart(char *command) { local_irq_disable(); #if 1 /* Resetting PCI bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ mdelay(1); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); #endif jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); /* fallback */ (*_machine_halt)(); }
static inline void do_reset(void) { #ifdef CONFIG_TC35815 extern void tc35815_killall(void); tc35815_killall(); #endif #if 1 /* Resetting PCI bus */ jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR); (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */ mdelay(1); jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); #endif jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR); }