/**
* @brief Calculate the derived properties
*
* Fill the base_gpu_props structure with values derived from the GPU configuration registers
*
* @param gpu_props The base_gpu_props structure
* @param kbdev The kbase_device structure for the device
*/
static void kbase_gpuprops_calculate_props(base_gpu_props * const gpu_props, kbase_device *kbdev)
{
int i;
/* Populate the base_gpu_props structure */
gpu_props->core_props.version_status = KBASE_UBFX32(gpu_props->raw_props.gpu_id, 0U, 4);
gpu_props->core_props.minor_revision = KBASE_UBFX32(gpu_props->raw_props.gpu_id, 4U, 8);
gpu_props->core_props.major_revision = KBASE_UBFX32(gpu_props->raw_props.gpu_id, 12U, 4);
gpu_props->core_props.product_id = KBASE_UBFX32(gpu_props->raw_props.gpu_id, 16U, 16);
gpu_props->core_props.log2_program_counter_size = KBASE_GPU_PC_SIZE_LOG2;
gpu_props->core_props.gpu_available_memory_size = totalram_pages << PAGE_SHIFT;
for (i = 0; i < BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS; i++)
gpu_props->core_props.texture_features[i] = gpu_props->raw_props.texture_features[i];
gpu_props->l2_props.log2_line_size = KBASE_UBFX32(gpu_props->raw_props.l2_features, 0U, 8);
gpu_props->l2_props.log2_cache_size = KBASE_UBFX32(gpu_props->raw_props.l2_features, 16U, 8);
gpu_props->l2_props.num_l2_slices = 1;
if (gpu_props->core_props.product_id == GPU_ID_PI_T76X) {
gpu_props->l2_props.num_l2_slices = KBASE_UBFX32(gpu_props->raw_props.mem_features, 8U, 4) + 1;
}
gpu_props->l3_props.log2_line_size = KBASE_UBFX32(gpu_props->raw_props.l3_features, 0U, 8);
gpu_props->l3_props.log2_cache_size = KBASE_UBFX32(gpu_props->raw_props.l3_features, 16U, 8);
gpu_props->tiler_props.bin_size_bytes = 1 << KBASE_UBFX32(gpu_props->raw_props.tiler_features, 0U, 6);
gpu_props->tiler_props.max_active_levels = KBASE_UBFX32(gpu_props->raw_props.tiler_features, 8U, 4);
if (gpu_props->raw_props.thread_max_threads == 0)
gpu_props->thread_props.max_threads = THREAD_MT_DEFAULT;
else
gpu_props->thread_props.max_threads = gpu_props->raw_props.thread_max_threads;
if (gpu_props->raw_props.thread_max_workgroup_size == 0)
gpu_props->thread_props.max_workgroup_size = THREAD_MWS_DEFAULT;
else
gpu_props->thread_props.max_workgroup_size = gpu_props->raw_props.thread_max_workgroup_size;
if (gpu_props->raw_props.thread_max_barrier_size == 0)
gpu_props->thread_props.max_barrier_size = THREAD_MBS_DEFAULT;
else
gpu_props->thread_props.max_barrier_size = gpu_props->raw_props.thread_max_barrier_size;
gpu_props->thread_props.max_registers = KBASE_UBFX32(gpu_props->raw_props.thread_features, 0U, 16);
gpu_props->thread_props.max_task_queue = KBASE_UBFX32(gpu_props->raw_props.thread_features, 16U, 8);
gpu_props->thread_props.max_thread_group_split = KBASE_UBFX32(gpu_props->raw_props.thread_features, 24U, 6);
gpu_props->thread_props.impl_tech = KBASE_UBFX32(gpu_props->raw_props.thread_features, 30U, 2);
/* If values are not specified, then use defaults */
if (gpu_props->thread_props.max_registers == 0) {
gpu_props->thread_props.max_registers = THREAD_MR_DEFAULT;
gpu_props->thread_props.max_task_queue = THREAD_MTQ_DEFAULT;
gpu_props->thread_props.max_thread_group_split = THREAD_MTGS_DEFAULT;
}
/* Initialize the coherent_group structure for each group */
kbase_gpuprops_construct_coherent_groups(gpu_props);
}
/**
* @brief Get the GPU configuration
*
* Fill the base_gpu_props structure with values from the GPU configuration registers
*
* @param gpu_props The base_gpu_props structure
* @param kbdev The kbase_device structure for the device
*/
static void kbase_gpuprops_get_props(base_gpu_props * gpu_props, kbase_device * kbdev)
{
kbase_gpuprops_regdump regdump;
int i;
OSK_ASSERT(NULL != kbdev);
OSK_ASSERT(NULL != gpu_props);
/* Dump relevant registers */
kbase_gpuprops_dump_registers(kbdev, ®dump);
/* Populate the base_gpu_props structure */
gpu_props->core_props.version_status = KBASE_UBFX32(regdump.gpu_id, 0U, 4);
gpu_props->core_props.minor_revision = KBASE_UBFX32(regdump.gpu_id, 4U, 8);
gpu_props->core_props.major_revision = KBASE_UBFX32(regdump.gpu_id, 12U, 4);
gpu_props->core_props.product_id = KBASE_UBFX32(regdump.gpu_id, 16U, 16);
gpu_props->core_props.log2_program_counter_size = KBASE_GPU_PC_SIZE_LOG2;
gpu_props->core_props.gpu_available_memory_size = totalram_pages << PAGE_SHIFT;
for(i = 0; i < BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS; i++)
{
gpu_props->core_props.texture_features[i] = regdump.texture_features[i];
}
gpu_props->l2_props.log2_line_size = KBASE_UBFX32(regdump.l2_features, 0U, 8);
gpu_props->l2_props.log2_cache_size = KBASE_UBFX32(regdump.l2_features, 16U, 8);
gpu_props->l3_props.log2_line_size = KBASE_UBFX32(regdump.l3_features, 0U, 8);
gpu_props->l3_props.log2_cache_size = KBASE_UBFX32(regdump.l3_features, 16U, 8);
gpu_props->tiler_props.bin_size_bytes = 1 << KBASE_UBFX32(regdump.tiler_features, 0U, 6);
gpu_props->tiler_props.max_active_levels = KBASE_UBFX32(regdump.tiler_features, 8U, 4);
gpu_props->raw_props.gpu_id = regdump.gpu_id;
gpu_props->raw_props.tiler_features = regdump.tiler_features;
gpu_props->raw_props.mem_features = regdump.mem_features;
gpu_props->raw_props.mmu_features = regdump.mmu_features;
gpu_props->raw_props.l2_features = regdump.l2_features;
gpu_props->raw_props.l3_features = regdump.l3_features;
gpu_props->raw_props.as_present = regdump.as_present;
gpu_props->raw_props.js_present = regdump.js_present;
gpu_props->raw_props.shader_present = ((u64)regdump.shader_present_hi << 32) + regdump.shader_present_lo;
gpu_props->raw_props.tiler_present = ((u64)regdump.tiler_present_hi << 32) + regdump.tiler_present_lo;
gpu_props->raw_props.l2_present = ((u64)regdump.l2_present_hi << 32) + regdump.l2_present_lo;
gpu_props->raw_props.l3_present = ((u64)regdump.l3_present_hi << 32) + regdump.l3_present_lo;
for(i = 0; i < MIDG_MAX_JOB_SLOTS; i++)
{
gpu_props->raw_props.js_features[i] = regdump.js_features[i];
}
/* Initialize the coherent_group structure for each group */
kbase_gpuprops_construct_coherent_groups(gpu_props);
}
