void kbase_platform_dvfs_set_level(kbase_device *kbdev, int level) { static int prev_level = -1; int f; if (level == prev_level) return; if (WARN_ON((level >= MALI_DVFS_STEP)||(level < 0))) panic("invalid level"); #ifdef CONFIG_MALI_T6XX_DVFS mutex_lock(&mali_set_clock_lock); #endif f = mali_dvfs_infotbl[level].mem_freq; if (level > prev_level) { exynos5_bus_mif_update(mem_freq_req, f); kbase_platform_dvfs_set_vol(mali_dvfs_infotbl[level].voltage); kbase_platform_dvfs_set_clock(kbdev, mali_dvfs_infotbl[level].clock); } else { kbase_platform_dvfs_set_clock(kbdev, mali_dvfs_infotbl[level].clock); kbase_platform_dvfs_set_vol(mali_dvfs_infotbl[level].voltage); exynos5_bus_mif_update(mem_freq_req, f); } #if defined(CONFIG_MALI_T6XX_DEBUG_SYS) && defined(CONFIG_MALI_T6XX_DVFS) update_time_in_state(prev_level); #endif prev_level = level; #ifdef CONFIG_MALI_T6XX_DVFS mutex_unlock(&mali_set_clock_lock); #endif }
void kbase_platform_dvfs_set_level(kbase_device *kbdev, int level) { static int prev_level = -1; int mif_qos, int_qos, cpu_qos; #ifdef MALI_DEBUG printk(KERN_INFO "\n[mali_devfreq]dvfs level:%d\n", level); #endif if (level == prev_level) return; if (WARN_ON((level >= MALI_DVFS_STEP) || (level < 0))) panic("invalid level"); #ifdef CONFIG_MALI_T6XX_DVFS mutex_lock(&mali_set_clock_lock); #endif sec_debug_aux_log(SEC_DEBUG_AUXLOG_CPU_BUS_CLOCK_CHANGE, "old:%7d new:%7d (G3D)", mali_dvfs_infotbl[prev_level].clock*1000, mali_dvfs_infotbl[level].clock*1000); mif_qos = mali_dvfs_infotbl[level].mem_freq; int_qos = mali_dvfs_infotbl[level].int_freq; cpu_qos = mali_dvfs_infotbl[level].cpu_freq; if (level > prev_level) { #if defined(CONFIG_ARM_EXYNOS5420_BUS_DEVFREQ) pm_qos_update_request(&exynos5_g3d_mif_qos, mif_qos); pm_qos_update_request(&exynos5_g3d_int_qos, int_qos); pm_qos_update_request(&exynos5_g3d_cpu_qos, cpu_qos); #endif kbase_platform_dvfs_set_vol(mali_dvfs_infotbl[level].voltage + gpu_voltage_margin); kbase_platform_dvfs_set_clock(kbdev, mali_dvfs_infotbl[level].clock); bts_change_g3d_state(mali_dvfs_infotbl[level].clock); } else { bts_change_g3d_state(mali_dvfs_infotbl[level].clock); kbase_platform_dvfs_set_clock(kbdev, mali_dvfs_infotbl[level].clock); kbase_platform_dvfs_set_vol(mali_dvfs_infotbl[level].voltage + gpu_voltage_margin); #if defined(CONFIG_ARM_EXYNOS5420_BUS_DEVFREQ) pm_qos_update_request(&exynos5_g3d_mif_qos, mif_qos); pm_qos_update_request(&exynos5_g3d_int_qos, int_qos); pm_qos_update_request(&exynos5_g3d_cpu_qos, cpu_qos); #endif } #if defined(CONFIG_MALI_T6XX_DEBUG_SYS) && defined(CONFIG_MALI_T6XX_DVFS) update_time_in_state(prev_level); #endif prev_level = level; #ifdef CONFIG_MALI_T6XX_DVFS mutex_unlock(&mali_set_clock_lock); #endif }