void __init lh7a400_init_irq (void) { int irq; INTC_INTENC = 0xffffffff; /* Disable all interrupts */ GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */ barrier (); for (irq = 0; irq < NR_IRQS; ++irq) { switch (irq) { case IRQ_GPIO0INTR: case IRQ_GPIO1INTR: case IRQ_GPIO2INTR: case IRQ_GPIO3INTR: case IRQ_GPIO4INTR: case IRQ_GPIO5INTR: case IRQ_GPIO6INTR: case IRQ_GPIO7INTR: set_irq_chip (irq, &lh7a400_gpio_chip); set_irq_handler (irq, do_level_IRQ); /* OK default */ break; default: set_irq_chip (irq, &lh7a400_internal_chip); set_irq_handler (irq, do_level_IRQ); } set_irq_flags (irq, IRQF_VALID); } lh7a40x_init_board_irq (); /* *** FIXME: the LH7a400 does use FIQ interrupts in some cases. For the time being, these are not initialized. */ /* init_FIQ(); */ }
void __init lh7a400_init_irq (void) { int irq; INTC_INTENC = 0xffffffff; /* Disable all interrupts */ GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */ barrier (); for (irq = 0; irq < NR_IRQS; ++irq) { switch (irq) { case IRQ_GPIO0INTR: case IRQ_GPIO1INTR: case IRQ_GPIO2INTR: case IRQ_GPIO3INTR: case IRQ_GPIO4INTR: case IRQ_GPIO5INTR: case IRQ_GPIO6INTR: case IRQ_GPIO7INTR: set_irq_chip (irq, &lh7a400_gpio_chip); set_irq_handler (irq, handle_level_irq); /* OK default */ break; default: set_irq_chip (irq, &lh7a400_internal_chip); set_irq_handler (irq, handle_level_irq); } set_irq_flags (irq, IRQF_VALID); } lh7a40x_init_board_irq (); /* init_FIQ(); */ }
void __init lh7a404_init_irq (void) { int irq; #if defined(CONFIG_ARCH_LH7A400) && defined(CONFIG_ARCH_LH7A404) #define NOP 0xe1a00000 /* mov r0, r0 */ branch_irq_lh7a400 = NOP; #endif VIC1_INTENCLR = 0xffffffff; VIC2_INTENCLR = 0xffffffff; VIC1_INTSEL = 0; /* All IRQs */ VIC2_INTSEL = 0; /* All IRQs */ VIC1_NVADDR = VA_VIC1DEFAULT; VIC2_NVADDR = VA_VIC2DEFAULT; VIC1_VECTADDR = 0; VIC2_VECTADDR = 0; GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */ barrier (); /* Install prioritized interrupts, if there are any. */ /* The | 0x20*/ for (irq = 0; irq < 16; ++irq) { (&VIC1_VAD0)[irq] = (irq < ARRAY_SIZE (irq_pri_vic1)) ? (irq_pri_vic1[irq] | VA_VECTORED) : 0; (&VIC1_VECTCNTL0)[irq] = (irq < ARRAY_SIZE (irq_pri_vic1)) ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0; (&VIC2_VAD0)[irq] = (irq < ARRAY_SIZE (irq_pri_vic2)) ? (irq_pri_vic2[irq] | VA_VECTORED) : 0; (&VIC2_VECTCNTL0)[irq] = (irq < ARRAY_SIZE (irq_pri_vic2)) ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0; } for (irq = 0; irq < NR_IRQS; ++irq) { switch (irq) { case IRQ_GPIO0INTR: case IRQ_GPIO1INTR: case IRQ_GPIO2INTR: case IRQ_GPIO3INTR: case IRQ_GPIO4INTR: case IRQ_GPIO5INTR: case IRQ_GPIO6INTR: case IRQ_GPIO7INTR: set_irq_chip (irq, irq < 32 ? &lh7a404_gpio_vic1_chip : &lh7a404_gpio_vic2_chip); set_irq_handler (irq, handle_level_irq); /* OK default */ break; default: set_irq_chip (irq, irq < 32 ? &lh7a404_vic1_chip : &lh7a404_vic2_chip); set_irq_handler (irq, handle_level_irq); } set_irq_flags (irq, IRQF_VALID); } lh7a40x_init_board_irq (); }