/*
* omap3_noncore_dpll_program - set non-core DPLL M,N values directly
* @clk: struct clk * of DPLL to set
* @m: DPLL multiplier to set
* @n: DPLL divider to set
* @freqsel: FREQSEL value to set
*
* Program the DPLL with the supplied M, N values, and wait for the DPLL to
* lock.. Returns -EINVAL upon error, or 0 upon success.
*/
static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
{
struct dpll_data *dd;
u32 v;
if (!clk)
return -EINVAL;
dd = clk->dpll_data;
if (!dd)
return -EINVAL;
/*
* According to the 12-5 CDP code from TI, "Limitation 2.5"
* on 3430ES1 prevents us from changing DPLL multipliers or dividers
* on DPLL4.
*/
if (omap_rev() == OMAP3430_REV_ES1_0 &&
!strcmp("dpll4_ck", clk->name)) {
printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
"silicon 'Limitation 2.5' on 3430ES1.\n");
return -EINVAL;
}
/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
_omap3_noncore_dpll_bypass(clk);
/* Set jitter correction */
v = cm_read_mod_reg(clk->prcm_mod, dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
cm_write_mod_reg(v, clk->prcm_mod, dd->control_reg);
/* Set DPLL multiplier, divider */
v = cm_read_mod_reg(clk->prcm_mod, dd->mult_div1_reg);
v &= ~(dd->mult_mask | dd->div1_mask);
v |= m << __ffs(dd->mult_mask);
v |= (n - 1) << __ffs(dd->div1_mask);
if (dd->jtype) {
u8 dco, sd_div;
lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
v &= ~(dd->dco_sel_mask | dd->sd_div_mask);
v |= dco << __ffs(dd->dco_sel_mask);
v |= sd_div << __ffs(dd->sd_div_mask);
}
cm_write_mod_reg(v, clk->prcm_mod, dd->mult_div1_reg);
/* We let the clock framework set the other output dividers later */
/* REVISIT: Set ramp-up delay? */
_omap3_noncore_dpll_lock(clk);
return 0;
}
/*
* omap3_noncore_dpll_program - set non-core DPLL M,N values directly
* @clk: struct clk * of DPLL to set
* @m: DPLL multiplier to set
* @n: DPLL divider to set
* @freqsel: FREQSEL value to set
*
* Program the DPLL with the supplied M, N values, and wait for the DPLL to
* lock.. Returns -EINVAL upon error, or 0 upon success.
*/
static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
{
struct dpll_data *dd = clk->dpll_data;
u32 v;
/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
_omap3_noncore_dpll_bypass(clk);
/* Set jitter correction. No jitter correction for OMAP4 and OMAP3630
* since those silicon do not have freqsel field */
if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
v = __raw_readl(dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
__raw_writel(v, dd->control_reg);
}
/* Set DPLL multiplier, divider */
v = __raw_readl(dd->mult_div1_reg);
v &= ~(dd->mult_mask | dd->div1_mask);
v |= m << __ffs(dd->mult_mask);
v |= (n - 1) << __ffs(dd->div1_mask);
__raw_writel(v, dd->mult_div1_reg);
/*
* XXX This code is not needed for 3430/AM35XX; can it be optimized
* out in non-multi-OMAP builds for those chips?
*/
if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) {
u8 dco, sd_div;
lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
/* XXX This probably will need revision for OMAP4 */
v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
| OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK);
v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
}
/* We let the clock framework set the other output dividers later */
/* REVISIT: Set ramp-up delay? */
_omap3_noncore_dpll_lock(clk);
return 0;
}
/*
* omap3_noncore_dpll_program - set non-core DPLL M,N values directly
* @clk: struct clk * of DPLL to set
* @m: DPLL multiplier to set
* @n: DPLL divider to set
* @freqsel: FREQSEL value to set
*
* Program the DPLL with the supplied M, N values, and wait for the DPLL to
* lock.. Returns -EINVAL upon error, or 0 upon success.
*/
static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
{
struct dpll_data *dd = clk->dpll_data;
u32 v;
/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
_omap3_noncore_dpll_bypass(clk);
/* Set jitter correction */
v = __raw_readl(dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
__raw_writel(v, dd->control_reg);
/* Set DPLL multiplier, divider */
v = __raw_readl(dd->mult_div1_reg);
v &= ~(dd->mult_mask | dd->div1_mask);
v |= m << __ffs(dd->mult_mask);
v |= (n - 1) << __ffs(dd->div1_mask);
if (dd->jtype) {
u8 dco, sd_div;
lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
v &= ~(dd->dco_sel_mask | dd->sd_div_mask);
v |= dco << __ffs(dd->dco_sel_mask);
v |= sd_div << __ffs(dd->sd_div_mask);
}
__raw_writel(v, dd->mult_div1_reg);
/* We let the clock framework set the other output dividers later */
/* REVISIT: Set ramp-up delay? */
_omap3_noncore_dpll_lock(clk);
return 0;
}
