예제 #1
0
static int disp_probe(struct platform_device *pdev)
{
    struct class_device;
	int ret;
	int i;
    int new_count;
    static unsigned int disp_probe_cnt = 0;

    if(disp_probe_cnt!=0)
    {
        return 0;
    }
    
    new_count = nr_dispsys_dev + 1;
    dispsys_dev = krealloc(dispsys_dev, 
        sizeof(struct dispsys_device) * new_count, GFP_KERNEL);
    if (!dispsys_dev) {
        DDPERR("Unable to allocate dispsys_dev\n");
        return -ENOMEM;
    }
	
    dispsys_dev = &(dispsys_dev[nr_dispsys_dev]);
    dispsys_dev->dev = &pdev->dev;

    /* iomap registers and irq*/
    for(i=0;i<DISP_REG_NUM;i++)
    {
		struct resource res;
        dispsys_dev->regs[i] = of_iomap(pdev->dev.of_node, i);
        if (!dispsys_dev->regs[i]) {
            DDPERR("Unable to ioremap registers, of_iomap fail, i=%d \n", i);
            return -ENOMEM;
        }
		dispsys_reg[i] = dispsys_dev->regs[i];
		/* check physical register */
		of_address_to_resource(pdev->dev.of_node, i, &res);
		if(ddp_reg_pa_base[i] != res.start)
			DDPERR("DT err, i=%d, module=%s, map_addr=%p, reg_pa=0x%x!=0x%pa\n", 
		            i, ddp_get_reg_module_name(i), dispsys_dev->regs[i],
		            ddp_reg_pa_base[i], &res.start);
		
        /* get IRQ ID and request IRQ */
        {
            dispsys_dev->irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
            dispsys_irq[i] = dispsys_dev->irq[i];

			if(disp_is_intr_enable(i)==1)
            {
                ret = request_irq(dispsys_dev->irq[i], (irq_handler_t)disp_irq_handler, 
                            IRQF_TRIGGER_NONE, ddp_get_reg_module_name(i),  NULL);  // IRQF_TRIGGER_NONE dose not take effect here, real trigger mode set in dts file
                if (ret) {
                    DDPERR("Unable to request IRQ, request_irq fail, i=%d, irq=%d \n", i, dispsys_dev->irq[i]);
                    return ret;
                }
	            DDPMSG("irq enabled, module=%s, irq=%d \n", ddp_get_reg_module_name(i), dispsys_dev->irq[i]);
            }
            
        }
        DDPMSG("DT, i=%d, module=%s, map_addr=%p, map_irq=%d, reg_pa=0x%x\n", 
            i, ddp_get_reg_module_name(i), dispsys_dev->regs[i], dispsys_dev->irq[i], 
            ddp_reg_pa_base[i]);
    }    
    nr_dispsys_dev = new_count;
    //mipi tx reg map here

	////// power on MMSYS for early porting
#ifdef CONFIG_FPGA_EARLY_PORTING
	printk("[DISP Probe] power MMSYS:0x%lx,0x%lx\n",DISP_REG_CONFIG_MMSYS_CG_CLR0,DISP_REG_CONFIG_MMSYS_CG_CLR1);
	DISP_REG_SET(0,DISP_REG_CONFIG_MMSYS_CG_CLR0,0xFFFFFFFF);
	DISP_REG_SET(0,DISP_REG_CONFIG_MMSYS_CG_CLR1,0xFFFFFFFF);
	DISP_REG_SET(0,DISPSYS_CONFIG_BASE + 0xC04,0x1C000);//fpga should set this register
#endif
	//////

	// init arrays
	ddp_path_init();

    // init M4U callback
#ifdef early_porting_by_k
    DDPMSG("register m4u callback\n");
    m4u_register_fault_callback(M4U_PORT_DISP_OVL0, disp_m4u_callback, 0);
    m4u_register_fault_callback(M4U_PORT_DISP_RDMA0, disp_m4u_callback, 0);
    m4u_register_fault_callback(M4U_PORT_DISP_WDMA0, disp_m4u_callback, 0);
    m4u_register_fault_callback(M4U_PORT_DISP_OVL1, disp_m4u_callback, 0);
    m4u_register_fault_callback(M4U_PORT_DISP_RDMA1, disp_m4u_callback, 0);
    m4u_register_fault_callback(M4U_PORT_DISP_WDMA1, disp_m4u_callback, 0);
#endif

	DDPMSG("dispsys probe done.\n");	
	//NOT_REFERENCED(class_dev);
	return 0;
}
예제 #2
0
static int disp_probe(struct platform_device *pdev)
{
    struct class_device;
	int ret;
	int i;
    int new_count;
    static unsigned int disp_probe_cnt = 0;

    if(disp_probe_cnt!=0)
    {
        return 0;
    }

#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && (CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
	disp_misc_dev.minor = MISC_DYNAMIC_MINOR;
	disp_misc_dev.name = "mtk_disp";
	disp_misc_dev.fops = &disp_fops;
	disp_misc_dev.parent = NULL;
	ret = misc_register(&disp_misc_dev);
	if (ret) {
		pr_err("disp: fail to create mtk_disp node\n");
		return ERR_PTR(ret);
	}

	// secure video path implementation: a physical address is allocated to place a handle for decryption buffer.
	init_tplay_handle(&(pdev->dev)); // non-zero value for valid VA
#endif
	
    new_count = nr_dispsys_dev + 1;
    dispsys_dev = krealloc(dispsys_dev, 
        sizeof(struct dispsys_device) * new_count, GFP_KERNEL);
    if (!dispsys_dev) {
        DDPERR("Unable to allocate dispsys_dev\n");
        return -ENOMEM;
    }
	
    dispsys_dev = &(dispsys_dev[nr_dispsys_dev]);
    dispsys_dev->dev = &pdev->dev;

    /* iomap registers and irq*/
    for(i=0;i<DISP_REG_NUM;i++)
    {
        dispsys_dev->regs[i] = of_iomap(pdev->dev.of_node, i);
        if (!dispsys_dev->regs[i]) {
            continue;  // skip
        }
		dispsys_reg[i] = dispsys_dev->regs[i];
        /* get IRQ ID and request IRQ */
        dispsys_dev->irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
        dispsys_irq[i] = dispsys_dev->irq[i];
        if (!dispsys_dev->irq[i]) {
            continue;  // skip
        }
        
        if(disp_is_intr_enable(i)==1)
        {
            ret = request_irq(dispsys_dev->irq[i], (irq_handler_t)disp_irq_handler, 
                        IRQF_TRIGGER_NONE, DISP_DEVNAME,  NULL);  // IRQF_TRIGGER_NONE dose not take effect here, real trigger mode set in dts file
            if (ret) {
                DDPERR("Unable to request IRQ, request_irq fail, i=%d, irq=%d \n", i, dispsys_dev->irq[i]);
                return ret;
            }
        }            

        DDPMSG("DT, i=%d, module=%s, map_addr=%p, map_irq=%d, reg_pa=0x%x, irq=%d \n", 
            i, ddp_get_reg_module_name(i), dispsys_dev->regs[i], dispsys_dev->irq[i], ddp_reg_pa_base[i], ddp_irq_num[i]);
    }    
    nr_dispsys_dev = new_count;
    //mipi tx reg map here
	dsi_reg_va = dispsys_reg[DISP_REG_DSI0];
    mipi_tx_reg = dispsys_reg[DISP_REG_MIPI];
	DPI_REG = (PDPI_REGS)dispsys_reg[DISP_REG_DPI0];

	////// power on MMSYS for early porting
#ifdef CONFIG_FPGA_EARLY_PORTING
	printk("[DISP Probe] power MMSYS:0x%lx,0x%lx\n",DISP_REG_CONFIG_MMSYS_CG_CLR0,DISP_REG_CONFIG_MMSYS_CG_CLR1);
	DISP_REG_SET(0,DISP_REG_CONFIG_MMSYS_CG_CLR0,0xFFFFFFFF);
	DISP_REG_SET(0,DISP_REG_CONFIG_MMSYS_CG_CLR1,0xFFFFFFFF);
	DISP_REG_SET(0,DISPSYS_CONFIG_BASE + 0xC00,0x0);//fpga should set this register
#endif
	//////
#ifdef MTKFB_NO_M4U
	DISP_REG_SET(0,DISP_REG_SMI_LARB_MMU_EN,0x0);//m4u disable
#endif

	// init arrays
	ddp_path_init();

    // init M4U callback
    DDPMSG("register m4u callback\n");
    m4u_register_fault_callback(M4U_PORT_DISP_OVL0, disp_m4u_callback, 0);
    m4u_register_fault_callback(M4U_PORT_DISP_RDMA0, disp_m4u_callback, 0);
    m4u_register_fault_callback(M4U_PORT_DISP_WDMA0, disp_m4u_callback, 0);
#if defined(MTK_FB_OVL1_SUPPORT)
    m4u_register_fault_callback(M4U_PORT_DISP_OVL1, disp_m4u_callback, 0);
#endif
#if defined(MTK_FB_RDMA1_SUPPORT)
    m4u_register_fault_callback(M4U_PORT_DISP_RDMA1, disp_m4u_callback, 0);
#endif


	DDPMSG("dispsys probe done.\n");	
	//NOT_REFERENCED(class_dev);

	// bus hang issue error intr enable
	// when MMSYS clock off but GPU/MJC/PWM clock on, avoid display hang and trigger error intr
	{
        DISP_REG_SET_FIELD(0, MMSYS_TO_MFG_TX_ERROR, DISP_REG_CONFIG_MMSYS_INTEN, 1);
        DISP_REG_SET_FIELD(0, MMSYS_TO_MJC_TX_ERROR, DISP_REG_CONFIG_MMSYS_INTEN, 1);
        DISP_REG_SET_FIELD(0, PWM0_APB_TX_ERROR, DISP_REG_CONFIG_MMSYS_INTEN, 1);
	}
	
    /* sysfs */
     DDPMSG("sysfs disp +");
    //add kobject
    if(kobject_init_and_add(&kdispobj, &disp_kobj_ktype, NULL, "disp") <0){
		DDPERR("fail to add disp\n");
		return -ENOMEM;
    }	
	
	return 0;
}
예제 #3
0
static int mjc_open(struct inode *pInode, struct file *pFile)
{
    unsigned long ulFlags;
    unsigned int u4efuse;
#ifdef CONFIG_MTK_SEGMENT_TEST	
	unsigned int u4TestValue;
#endif
    
    MJCDBG("mjc_open() pid = %d\n", current->pid);

#ifndef CONFIG_MTK_SEGMENT_TEST	
    u4efuse = get_devinfo_with_index(EFUSE_MJC_IDX);
     
    if ((u4efuse & EFUSE_MJC_BIT) != 0)
    {
    	  MJCMSG("[ERROR] mjc efuse no support %d\n", u4efuse);
        return -1;
    }
#endif	

    // Gary todo: enable clock 
    enable_clock(MT_CG_DISP0_SMI_COMMON, "mjc");
	enable_clock(MT_CG_DISP0_LARB4_AXI_ASIF_MM, "mjc");
	enable_clock(MT_CG_DISP0_LARB4_AXI_ASIF_MJC, "mjc");
    enable_clock(MT_CG_MJC_SMI_LARB, "mjc");
	enable_clock(MT_CG_MJC_TOP_GROUP0, "mjc");
	enable_clock(MT_CG_MJC_TOP_GROUP1, "mjc");
	enable_clock(MT_CG_MJC_TOP_GROUP2, "mjc");
	enable_clock(MT_CG_MJC_LARB4_AXI_ASIF, "mjc");	

#ifdef CONFIG_MTK_SEGMENT_TEST
    u4TestValue = MJC_Reg32((gulRegister+4));
	MJCDBG("Pre-Read: 0x%x\n", u4TestValue);
	MJC_WriteReg32((gulRegister+4), 0x123456);
    MJC_WriteReg32((gulRegister+4), 0x123456);
	u4TestValue = MJC_Reg32((gulRegister+4));
	MJCDBG("Read: 0x%x\n", u4TestValue);
	if (u4TestValue == 0x123456)
	{
	    MJCMSG("[MJC efuse] HW enable\n");
	}
	else
	{
	    MJCMSG("[MJC efuse] HW disable\n");
		return -1;
	}
#endif	

	spin_lock_irqsave(&ContextLock, ulFlags);
	grContext.rEvent.u4TimeoutMs = 0xFFFFFFFF;
	spin_unlock_irqrestore(&ContextLock, ulFlags);

	spin_lock_irqsave(&HWLock, ulFlags);
	grHWLockContext.rEvent.u4TimeoutMs = 0xFFFFFFFF;
	spin_unlock_irqrestore(&HWLock, ulFlags);

	_mjc_m4uConfigPort();

	m4u_register_fault_callback(M4U_PORT_MJC_MV_RD, mjc_m4u_fault_callback, (void *)0);
	m4u_register_fault_callback(M4U_PORT_MJC_MV_WR, mjc_m4u_fault_callback, (void *)0);
	m4u_register_fault_callback(M4U_PORT_MJC_DMA_RD, mjc_m4u_fault_callback, (void *)0);
	m4u_register_fault_callback(M4U_PORT_MJC_DMA_WR, mjc_m4u_fault_callback, (void *)0);

	MJCDBG("Mapping register: 0x%lx, PA:0x%lx, Size:0x%lx, Irq ID:%d\n", gulRegister, gu1PaReg, gu1PaSize, gi4IrqID);

	return 0;
}