/* We also own one page of host buffer space for the allocation of * UART "fifos" and the like. */ uint m8560_cpm_hostalloc(uint size, uint align) { /* the host might not even have RAM yet - just use dual port RAM */ return (m8560_cpm_dpalloc(size, align)); }
int serial_init (void) { volatile immap_t *im = (immap_t *)CFG_IMMR; volatile ccsr_cpm_scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp); uint dpaddr; /* initialize pointers to SCC */ sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]); up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); /* Disable transmitter/receiver. */ sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); /* put the SCC channel into NMSI (non multiplexd serial interface) * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). */ im->im_cpm.im_cpm_mux.cmxscr = \ (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; /* Set up the baud rate generator. */ serial_setbrg (); /* Allocate space for two buffer descriptors in the DP ram. * damm: allocating space after the two buffers for rx/tx data */ dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); /* Set the physical address of the host memory buffers in * the buffer descriptors. */ rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]); rbdf->cbd_bufaddr = (uint) (rbdf+2); rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; tbdf = rbdf + 1; tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; tbdf->cbd_sc = BD_SC_WRAP; /* Set up the uart parameters in the parameter ram. */ up->scc_genscc.scc_rbase = dpaddr; up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); up->scc_genscc.scc_rfcr = CPMFCR_EB; up->scc_genscc.scc_tfcr = CPMFCR_EB; up->scc_genscc.scc_mrblr = 1; up->scc_maxidl = 0; up->scc_brkcr = 1; up->scc_parec = 0; up->scc_frmec = 0; up->scc_nosec = 0; up->scc_brkec = 0; up->scc_uaddr1 = 0; up->scc_uaddr2 = 0; up->scc_toseq = 0; up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000; up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000; up->scc_rccm = 0xc0ff; /* Mask all interrupts and remove anything pending. */ sp->sccm = 0; sp->scce = 0xffff; /* Set 8 bit FIFO, 16 bit oversampling and UART mode. */ sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */ sp->gsmrl = \ SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART; /* Set CTS no flow control, 1 stop bit, 8 bit character length, * normal async UART mode, no parity */ sp->psmr = SCU_PSMR_CL; /* execute the "Init Rx and Tx params" CP command. */ while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; /* Enable transmitter/receiver. */ sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT; return (0); }