/* The port B alternate register is an alternate register for reading the port B pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
the instantaneous pin level is read and no input latching is performed except at the
data bus interface.Writes to this address are answered with DTACK, but the data is ignored.*/
uint8_t pit68230_device::rr_pitreg_pbar()
{
uint8_t ret;
ret = m_pb_in_cb.isnull() ? 0 : m_pb_in_cb();
LOGR("%s %s <- %02x\n",tag(), FUNCNAME, ret);
return ret;
}
/* The port B alternate register is an alternate register for reading the port B pins.
It is a read-only address and no other PI/T condition is affected. In all modes,
the instantaneous pin level is read and no input latching is performed except at the
data bus interface.Writes to this address are answered with DTACK, but the data is ignored.*/
UINT8 pit68230_device::rr_pitreg_pbar()
{
// NOTE: no side effect emulated so using ..pbdr
UINT8 ret;
ret = m_pb_in_cb();
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, ret));
return ret;
}
/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding
* register for moving data to and from port B pins. The port B data direction
* register determines whether each pin is an input (zero) or an output (one).
* This register is readable and writable at all times. Depending on the chosen
* mode/submode, reading or writing may affect the double-buffered handshake
* mechanism. The port B data register is not affected by the assertion of the
* RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
uint8_t pit68230_device::rr_pitreg_pbdr()
{
m_pbdr &= m_pbddr;
if (!m_pb_in_cb.isnull())
{
m_pbdr |= (m_pb_in_cb() & ~m_pbddr);
}
else
{
m_pbdr |= (m_pbil & ~m_pbddr);
}
LOGDR("%s %s <- %02x\n",tag(), FUNCNAME, m_pbdr);
return m_pbdr;
}
