int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
initializeClocks();
InitializeButton();
InitializeLeds();
//This will reset the nRF8001. ACI Device Started Event is generated by the nRF8001 device
//as soon as the reset is complete
hal_aci_tl_init();
// Reset nRF8001
resetDevice();
_BIS_SR(GIE);
begin_BLE(&aci_state);
// Main application loop
for (;;)
{
//_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/interrupt
_nop(); // For debugger
//Not entirely sure if any of this if statement needs to be here...
if(rdynFlag == 1)
{
rdynFlag = 0;
m_rdy_line_handle();
}
pollACI(&aci_state, &aci_data, &aci_cmd);
state = getState();
if ((getState() == ACI_EVT_CONNECTED) && (!ctr) && lib_aci_is_pipe_available(&aci_state, PIPE_UART_OVER_BTLE_UART_TX_TX)) {
//make sure pipe is available
//#define UART
#ifdef UART
write("80 98 37 998", 12, &aci_state, &aci_data, &aci_cmd);
#else
write(data, 6, &aci_state, &aci_data, &aci_cmd);
#endif
//lib_aci_get_battery_level();
}
ctr++;
}
}
bool lib_aci_event_get(aci_state_t *aci_stat, hal_aci_evt_t *p_aci_evt_data)
{
bool status = false;
if (false == aci_stat->aci_pins.interface_is_interrupt)
{
/*
Check the RDYN line
When the RDYN line goes low
Run the SPI master
place the returned ACI Event in the p_aci_evt_data
*/
/*
When the RDYN goes low it means the nRF8001 is ready for the SPI transaction
*/
if (0 != digitalRead(aci_stat->aci_pins.rdyn_pin))
{
/* RDYN line was not low */
/*when there are commands in the Command queue. place the REQN line low, so the RDYN line will go low later*/
if ((false == m_aci_q_is_empty(&aci_tx_q)) &&
(false == m_aci_q_is_full(&aci_rx_q)))
{
digitalWrite(aci_stat->aci_pins.reqn_pin, 0);
}
/*
Master SPI cannot be run , no event to process
*/
}
else
{
/*
Now process the Master SPI
*/
m_rdy_line_handle();
}
}
status = hal_aci_tl_event_get((hal_aci_data_t *)p_aci_evt_data);
/**
Update the state of the ACI witn the
ACI Events -> Pipe Status, Disconnected, Connected, Bond Status, Pipe Error
*/
if (true == status)
{
aci_evt_t * aci_evt;
aci_evt = &p_aci_evt_data->evt;
switch(aci_evt->evt_opcode)
{
case ACI_EVT_PIPE_STATUS:
{
uint8_t i=0;
for (i=0; i < PIPES_ARRAY_SIZE; i++)
{
aci_stat->pipes_open_bitmap[i] = aci_evt->params.pipe_status.pipes_open_bitmap[i];
aci_stat->pipes_closed_bitmap[i] = aci_evt->params.pipe_status.pipes_closed_bitmap[i];
}
}
break;
case ACI_EVT_DISCONNECTED:
{
uint8_t i=0;
for (i=0; i < PIPES_ARRAY_SIZE; i++)
{
aci_stat->pipes_open_bitmap[i] = 0;
aci_stat->pipes_closed_bitmap[i] = 0;
}
aci_stat->confirmation_pending = false;
aci_stat->data_credit_available = aci_stat->data_credit_total;
}
break;
case ACI_EVT_TIMING:
aci_stat->connection_interval = aci_evt->params.timing.conn_rf_interval;
aci_stat->slave_latency = aci_evt->params.timing.conn_slave_rf_latency;
aci_stat->supervision_timeout = aci_evt->params.timing.conn_rf_timeout;
break;
}
}
return status;
}