void namco_c117_device::register_w(int whichcpu, offs_t offset, uint8_t data)
{
int reg = (offset >> 9) & 0xf;
bool unknown_reg = false;
switch (reg)
{
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
bankswitch(whichcpu, reg, offset & 1, data);
break;
case 8: // F000 - SUBRES (halt/reset everything but main CPU)
if (whichcpu == 0)
{
m_subres = data & 1;
m_subres_cb(m_subres ? CLEAR_LINE : ASSERT_LINE);
}
else
unknown_reg = true;
break;
case 9: // F200 - kick watchdog
kick_watchdog(whichcpu);
break;
// case 10: // F400 - unknown but used
// break;
case 11: // F600 - IRQ ack
m_cpuexec[whichcpu]->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
break;
case 12: // F800 - FIRQ ack
m_cpuexec[whichcpu]->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
break;
case 13: // FA00 - assert FIRQ on sub CPU
if (whichcpu == 0)
m_cpuexec[1]->set_input_line(M6809_FIRQ_LINE, ASSERT_LINE);
else
unknown_reg = true;
break;
case 14: // FC00 - set initial ROM bank for sub CPU
if (whichcpu == 0)
{
m_offsets[1][7] = 0x600000 | (data * 0x2000);
m_cpudirect[1]->force_update();
}
else
unknown_reg = true;
break;
default:
unknown_reg = true;
}
if (unknown_reg)
logerror("'%s' writing to unknown CUS117 register %04X = %02X\n", (whichcpu ? m_subcpu_tag : m_maincpu_tag), offset, data);
}
void namco_c117_device::device_reset()
{
// default MMU setup for main CPU
m_offsets[0][0] = 0x0180 * 0x2000; // bank0 = 0x180(RAM) - evidence: wldcourt
m_offsets[0][1] = 0x0180 * 0x2000; // bank1 = 0x180(RAM) - evidence: berabohm
m_offsets[0][7] = 0x03ff * 0x2000; // bank7 = 0x3ff(PRG7)
// default MMU setup for sub CPU
m_offsets[1][0] = 0x0180 * 0x2000; // bank0 = 0x180(RAM) - evidence: wldcourt
m_offsets[1][7] = 0x03ff * 0x2000; // bank7 = 0x3ff(PRG7)
m_subres = m_wdog = 0;
m_subres_cb(ASSERT_LINE);
// reset the main CPU so it picks up the reset vector from the correct bank
m_cpuexec[0]->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
}
