void e40::internal_loopback(uint32_t instance)
{
gen_ctrl_ = 0;
mon_ctrl_ = 0;
auto mac0 = read_mac_address(0);
auto mac_ctrl = instance == 0 ? mac_reg::mac0_ctrl : mac_reg::mac1_ctrl;
if (packet_count_ > 0)
{
eth_->write(eth_ctrl_reg::gen_pkt_number, instance, packet_count_);
eth_->write(eth_ctrl_reg::mon_pkt_number, instance, packet_count_);
}
else
{
mon_ctrl_ |= static_cast<uint32_t>(gen_ctrl::continuous);
gen_ctrl_ |= static_cast<uint32_t>(gen_ctrl::continuous);
}
mac_write(mac_ctrl, mac_reg::mac_srl_lpbk_ctrl, 0x3FF);
mac_write(mac_ctrl, mac_reg::mac_cntr_tx_ctrl, 1);
mac_write(mac_ctrl, mac_reg::mac_cntr_rx_ctrl, 1);
eth_->write(eth_ctrl_reg::gen_src_addr_l, instance, mac0.lo);
eth_->write(eth_ctrl_reg::gen_src_addr_h, instance, mac0.hi);
eth_->write(eth_ctrl_reg::mon_src_addr_l, instance, mac0.lo);
eth_->write(eth_ctrl_reg::mon_src_addr_h, instance, mac0.hi);
eth_->write(eth_ctrl_reg::gen_dst_addr_l, instance, mac0.lo);
eth_->write(eth_ctrl_reg::gen_dst_addr_h, instance, mac0.hi);
eth_->write(eth_ctrl_reg::mon_dst_addr_l, instance, mac0.lo);
eth_->write(eth_ctrl_reg::mon_dst_addr_h, instance, mac0.hi);
eth_->write(eth_ctrl_reg::mon_pkt_ctrl, instance, mon_ctrl_ | static_cast<uint32_t>(mon_ctrl::start));
eth_->write(eth_ctrl_reg::gen_pkt_ctrl, instance, gen_ctrl_ | static_cast<uint32_t>(gen_ctrl::start));
}
void e40::clear_status()
{
mac_write(mac_reg::mac0_ctrl, mac_reg::mac_cntr_tx_ctrl, 1);
mac_write(mac_reg::mac0_ctrl, mac_reg::mac_cntr_rx_ctrl, 1);
mac_write(mac_reg::mac1_ctrl, mac_reg::mac_cntr_tx_ctrl, 1);
mac_write(mac_reg::mac1_ctrl, mac_reg::mac_cntr_rx_ctrl, 1);
}
int
net_s3c4510b_write_word (struct device_desc *dev, u32 addr, u32 data)
{
struct net_device *net_dev = (struct net_device *) dev->dev;
struct net_s3c4510b_io *io = (struct net_s3c4510b_io *) dev->data;
int offset = (u16) (addr - dev->base + 0x9000);
int ret = ADDR_HIT;
//printf("%s\n", __FUNCTION__);
switch (offset) {
case MACTXCON:
if (data & TxEn == TxEn) {
/*
u32 addr;
fault_t fault;
fault = mac_write(dev);
if( fault ) {
mmu_data_abort(state, fault, addr);
return;
}
*/
mac_write (dev);
}
io->mactxcon = data;
break;
case BDMATXPTR:
io->bdmatxptr = data;
break;
case BDMARXPTR:
io->bdmarxptr = data;
break;
case BDMASTAT:
io->bdmastat &= (~data);
break;
case MACON:
io->macon = data;
break;
case MACRXCON:
io->macrxcon = data;
break;
case BDMARXCON:
io->bdmarxcon = data;
break;
case BDMATXCON:
io->bdmatxcon = data;
break;
case BDMARXLSZ:
io->bdmarxlsz = data;
break;
case CAMEN:
io->camen = data;
break;
default:
break;
}
return ret;
}
int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
unsigned char mac[6];
char *s, *e;
if (argc != 2)
return cmd_usage(cmdtp);
s = argv[1];
for (i = 0; i < 6; i++) {
mac[i] = s ? simple_strtoul(s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
mac_write((unsigned short *)mac);
return 0;
}
void e40::external_loopback(uint32_t source_port, uint32_t destination_port)
{
auto mac0 = read_mac_address(source_port);
auto mac1 = read_mac_address(destination_port);
gen_ctrl_ = 0;
mon_ctrl_ = 0;
if (random_length_)
{
gen_ctrl_ |= static_cast<uint32_t>(gen_ctrl::random_packet_length);
}
if (continuous_)
{
gen_ctrl_ |= static_cast<uint32_t>(gen_ctrl::continuous);
mon_ctrl_ |= static_cast<uint32_t>(mon_ctrl::continuous);
}
else
{
if (packet_count_ > 0)
{
eth_->write(eth_ctrl_reg::gen_pkt_number, source_port, packet_count_);
eth_->write(eth_ctrl_reg::mon_pkt_number, destination_port, packet_count_);
}
}
if (packet_length_ > 0) eth_->write(eth_ctrl_reg::gen_pkt_length, source_port, packet_length_);
if (packet_delay_ > 0) eth_->write(eth_ctrl_reg::gen_pkt_delay, source_port, packet_delay_);
// turn off serial loopback
mac_write(mac_reg::mac0_ctrl, mac_reg::mac_srl_lpbk_ctrl, 0x0);
mac_write(mac_reg::mac1_ctrl, mac_reg::mac_srl_lpbk_ctrl, 0x0);
// PORT 0 GEN SRC -> MAC0
eth_->write(eth_ctrl_reg::gen_src_addr_l, source_port, mac0.lo);
eth_->write(eth_ctrl_reg::gen_src_addr_h, source_port, mac0.hi);
// PORT 0 GEN DST -> MAC1
eth_->write(eth_ctrl_reg::gen_dst_addr_l, source_port, mac1.lo);
eth_->write(eth_ctrl_reg::gen_dst_addr_h, source_port, mac1.hi);
// PORT 0 MON SRC -> MAC1
eth_->write(eth_ctrl_reg::mon_src_addr_l, source_port, mac1.lo);
eth_->write(eth_ctrl_reg::mon_src_addr_h, source_port, mac1.hi);
// PORT 0 MON DST -> MAC0
eth_->write(eth_ctrl_reg::mon_dst_addr_l, source_port, mac0.lo);
eth_->write(eth_ctrl_reg::mon_dst_addr_h, source_port, mac0.hi);
// PORT 1 GEN SRC -> MAC1
eth_->write(eth_ctrl_reg::gen_src_addr_l, destination_port, mac1.lo);
eth_->write(eth_ctrl_reg::gen_src_addr_h, destination_port, mac1.hi);
// PORT 1 GEN SRC -> MAC0
eth_->write(eth_ctrl_reg::gen_dst_addr_l, destination_port, mac0.lo);
eth_->write(eth_ctrl_reg::gen_dst_addr_h, destination_port, mac0.hi);
// PORT 1 MON SRC -> MAC0
eth_->write(eth_ctrl_reg::mon_src_addr_l, destination_port, mac0.lo);
eth_->write(eth_ctrl_reg::mon_src_addr_h, destination_port, mac0.hi);
// PORT 1 MON DST -> MAC1
eth_->write(eth_ctrl_reg::mon_dst_addr_l, destination_port, mac1.lo);
eth_->write(eth_ctrl_reg::mon_dst_addr_h, destination_port, mac1.hi);
eth_->write(eth_ctrl_reg::mon_pkt_ctrl, destination_port, mon_ctrl_ | static_cast<uint32_t>(mon_ctrl::start));
eth_->write(eth_ctrl_reg::gen_pkt_ctrl, source_port, gen_ctrl_ | static_cast<uint32_t>(gen_ctrl::start));
}
